d1vga_control     894 drivers/gpu/drm/amd/amdgpu/cik.c 	u32 d1vga_control = 0;
d1vga_control     902 drivers/gpu/drm/amd/amdgpu/cik.c 		d1vga_control = RREG32(mmD1VGA_CONTROL);
d1vga_control     913 drivers/gpu/drm/amd/amdgpu/cik.c 		       (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
d1vga_control     928 drivers/gpu/drm/amd/amdgpu/cik.c 		WREG32(mmD1VGA_CONTROL, d1vga_control);
d1vga_control     666 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
d1vga_control     669 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
d1vga_control     822 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
d1vga_control     825 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
d1vga_control     942 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
d1vga_control     945 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
d1vga_control    1060 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
d1vga_control    1063 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
d1vga_control    1138 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	u32 d1vga_control;
d1vga_control    1148 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
d1vga_control    1149 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
d1vga_control    1114 drivers/gpu/drm/amd/amdgpu/si.c 	u32 d1vga_control = 0;
d1vga_control    1122 drivers/gpu/drm/amd/amdgpu/si.c 		d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
d1vga_control    1133 drivers/gpu/drm/amd/amdgpu/si.c 		       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
d1vga_control    1148 drivers/gpu/drm/amd/amdgpu/si.c 		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
d1vga_control     378 drivers/gpu/drm/amd/amdgpu/vi.c 	u32 d1vga_control = 0;
d1vga_control     386 drivers/gpu/drm/amd/amdgpu/vi.c 		d1vga_control = RREG32(mmD1VGA_CONTROL);
d1vga_control     397 drivers/gpu/drm/amd/amdgpu/vi.c 		       (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
d1vga_control     412 drivers/gpu/drm/amd/amdgpu/vi.c 		WREG32(mmD1VGA_CONTROL, d1vga_control);
d1vga_control     254 drivers/gpu/drm/radeon/radeon_bios.c 	u32 d1vga_control;
d1vga_control     261 drivers/gpu/drm/radeon/radeon_bios.c 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
d1vga_control     271 drivers/gpu/drm/radeon/radeon_bios.c 		       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
d1vga_control     286 drivers/gpu/drm/radeon/radeon_bios.c 		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
d1vga_control     298 drivers/gpu/drm/radeon/radeon_bios.c 	uint32_t d1vga_control;
d1vga_control     308 drivers/gpu/drm/radeon/radeon_bios.c 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
d1vga_control     319 drivers/gpu/drm/radeon/radeon_bios.c 	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
d1vga_control     356 drivers/gpu/drm/radeon/radeon_bios.c 	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
d1vga_control     367 drivers/gpu/drm/radeon/radeon_bios.c 	uint32_t d1vga_control;
d1vga_control     381 drivers/gpu/drm/radeon/radeon_bios.c 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
d1vga_control     398 drivers/gpu/drm/radeon/radeon_bios.c 	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
d1vga_control     427 drivers/gpu/drm/radeon/radeon_bios.c 	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
d1vga_control     445 drivers/gpu/drm/radeon/radeon_bios.c 	uint32_t d1vga_control;
d1vga_control     456 drivers/gpu/drm/radeon/radeon_bios.c 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
d1vga_control     478 drivers/gpu/drm/radeon/radeon_bios.c 	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
d1vga_control     492 drivers/gpu/drm/radeon/radeon_bios.c 	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);