d1_display_write_back_dwb_enable 200 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h DC_LOG_BANDWIDTH_CALCS(" [bool] d1_display_write_back_dwb_enable: %d", data->d1_display_write_back_dwb_enable); d1_display_write_back_dwb_enable 351 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->d1_display_write_back_dwb_enable == 1) { d1_display_write_back_dwb_enable 497 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) { d1_display_write_back_dwb_enable 1189 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->d1_display_write_back_dwb_enable == 1) { d1_display_write_back_dwb_enable 1951 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->d1_display_write_back_dwb_enable == 1) { d1_display_write_back_dwb_enable 1977 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->d1_display_write_back_dwb_enable == 1) { d1_display_write_back_dwb_enable 247 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool d1_display_write_back_dwb_enable;