DIG_FE_CNTL       536 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	} else if (enc110->regs->DIG_FE_CNTL) {
DIG_FE_CNTL       539 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
DIG_FE_CNTL       542 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
DIG_FE_CNTL       545 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
DIG_FE_CNTL       579 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	} else if (enc110->regs->DIG_FE_CNTL) {
DIG_FE_CNTL      1008 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
DIG_FE_CNTL      1592 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
DIG_FE_CNTL      1593 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
DIG_FE_CNTL      1602 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
DIG_FE_CNTL      1611 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
DIG_FE_CNTL        67 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SRI(DIG_FE_CNTL, DIG, id), \
DIG_FE_CNTL       168 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
DIG_FE_CNTL       169 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
DIG_FE_CNTL       170 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
DIG_FE_CNTL       203 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
DIG_FE_CNTL       304 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
DIG_FE_CNTL       305 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
DIG_FE_CNTL       306 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
DIG_FE_CNTL       307 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
DIG_FE_CNTL       314 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
DIG_FE_CNTL       315 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
DIG_FE_CNTL       657 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	uint32_t DIG_FE_CNTL;
DIG_FE_CNTL       482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
DIG_FE_CNTL       485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
DIG_FE_CNTL       488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
DIG_FE_CNTL       975 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
DIG_FE_CNTL      1532 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
DIG_FE_CNTL      1533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
DIG_FE_CNTL      1542 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
DIG_FE_CNTL      1551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
DIG_FE_CNTL        54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	SRI(DIG_FE_CNTL, DIG, id), \
DIG_FE_CNTL       123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	uint32_t DIG_FE_CNTL;
DIG_FE_CNTL       400 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 				REG_UPDATE(DIG_FE_CNTL,
DIG_FE_CNTL       416 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 			REG_UPDATE(DIG_FE_CNTL,
DIG_FE_CNTL       500 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
DIG_FE_CNTL       505 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);