DIG_BE_CNTL 576 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); DIG_BE_CNTL 887 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); DIG_BE_CNTL 891 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); DIG_BE_CNTL 896 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); DIG_BE_CNTL 900 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); DIG_BE_CNTL 904 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); DIG_BE_CNTL 1358 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); DIG_BE_CNTL 1365 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); DIG_BE_CNTL 51 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SRI(DIG_BE_CNTL, DIG, id), \ DIG_BE_CNTL 131 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t DIG_BE_CNTL; DIG_BE_CNTL 456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); DIG_BE_CNTL 564 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); DIG_BE_CNTL 881 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); DIG_BE_CNTL 885 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); DIG_BE_CNTL 890 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); DIG_BE_CNTL 894 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); DIG_BE_CNTL 898 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); DIG_BE_CNTL 1325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); DIG_BE_CNTL 1332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); DIG_BE_CNTL 1407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_MODE, &value); DIG_BE_CNTL 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h SRI(DIG_BE_CNTL, DIG, id), \ DIG_BE_CNTL 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t DIG_BE_CNTL;