cur_value 1084 drivers/crypto/qat/qat_common/qat_hal.c unsigned int cur_value; cur_value 1091 drivers/crypto/qat/qat_common/qat_hal.c cur_value = value[0]; cur_value 1101 drivers/crypto/qat/qat_common/qat_hal.c INSERT_IMMED_GPRB_CONST(micro_inst[fixup_offset], (cur_value >> 0)); cur_value 1103 drivers/crypto/qat/qat_common/qat_hal.c INSERT_IMMED_GPRB_CONST(micro_inst[fixup_offset], (cur_value >> 0x10)); cur_value 76 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c uint32_t cur_value; cur_value 78 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); cur_value 79 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c if (cur_value > dlg_attr->refcyc_per_vm_group_vblank) cur_value 85 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c &cur_value); cur_value 86 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c if (cur_value > dlg_attr->refcyc_per_vm_req_vblank) cur_value 90 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); cur_value 91 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c if (cur_value > dlg_attr->refcyc_per_vm_group_flip) cur_value 95 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); cur_value 96 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c if (cur_value > dlg_attr->refcyc_per_vm_req_flip) cur_value 113 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t cur_value; cur_value 121 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c cur_value = cgs_read_register(hwmgr->device, index); cur_value 122 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c if ((cur_value & mask) == (value & mask)) cur_value 159 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t cur_value; cur_value 165 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c cur_value = cgs_read_register(hwmgr->device, cur_value 167 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c if ((cur_value & mask) != (value & mask)) cur_value 687 drivers/gpu/drm/amd/powerplay/navi10_ppt.c uint32_t cur_value = 0, value = 0, count = 0; cur_value 699 drivers/gpu/drm/amd/powerplay/navi10_ppt.c ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); cur_value 704 drivers/gpu/drm/amd/powerplay/navi10_ppt.c cur_value = cur_value / 100; cur_value 717 drivers/gpu/drm/amd/powerplay/navi10_ppt.c cur_value == value ? "*" : ""); cur_value 727 drivers/gpu/drm/amd/powerplay/navi10_ppt.c freq_values[1] = cur_value; cur_value 728 drivers/gpu/drm/amd/powerplay/navi10_ppt.c mark_index = cur_value == freq_values[0] ? 0 : cur_value 729 drivers/gpu/drm/amd/powerplay/navi10_ppt.c cur_value == freq_values[2] ? 2 : 1; cur_value 184 drivers/gpu/drm/amd/powerplay/renoir_ppt.c uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; cur_value 203 drivers/gpu/drm/amd/powerplay/renoir_ppt.c cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; cur_value 207 drivers/gpu/drm/amd/powerplay/renoir_ppt.c if (cur_value == max) cur_value 209 drivers/gpu/drm/amd/powerplay/renoir_ppt.c else if (cur_value == min) cur_value 217 drivers/gpu/drm/amd/powerplay/renoir_ppt.c i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, cur_value 225 drivers/gpu/drm/amd/powerplay/renoir_ppt.c cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; cur_value 229 drivers/gpu/drm/amd/powerplay/renoir_ppt.c cur_value = metrics.ClockFrequency[CLOCK_UMCCLK]; cur_value 233 drivers/gpu/drm/amd/powerplay/renoir_ppt.c cur_value = metrics.ClockFrequency[CLOCK_DCFCLK]; cur_value 237 drivers/gpu/drm/amd/powerplay/renoir_ppt.c cur_value = metrics.ClockFrequency[CLOCK_FCLK]; cur_value 246 drivers/gpu/drm/amd/powerplay/renoir_ppt.c cur_value == value ? "*" : ""); cur_value 247 drivers/gpu/drm/amd/powerplay/renoir_ppt.c if (cur_value == value) cur_value 252 drivers/gpu/drm/amd/powerplay/renoir_ppt.c size += sprintf(buf + size, " %uMhz *\n", cur_value); cur_value 75 drivers/gpu/drm/amd/powerplay/smu_v11_0.c uint32_t cur_value, i, timeout = adev->usec_timeout * 10; cur_value 78 drivers/gpu/drm/amd/powerplay/smu_v11_0.c cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); cur_value 79 drivers/gpu/drm/amd/powerplay/smu_v11_0.c if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0) cur_value 64 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t cur_value, i; cur_value 67 drivers/gpu/drm/amd/powerplay/smu_v12_0.c cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); cur_value 68 drivers/gpu/drm/amd/powerplay/smu_v12_0.c if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0) cur_value 608 drivers/input/touchscreen/wdt87xx_i2c.c static u16 misr(u16 cur_value, u8 new_value) cur_value 614 drivers/input/touchscreen/wdt87xx_i2c.c a = cur_value; cur_value 2073 drivers/net/ethernet/qlogic/qed/qed_main.c u32 offset, mask, value, cur_value; cur_value 2091 drivers/net/ethernet/qlogic/qed/qed_main.c cur_value = le32_to_cpu(*((__le32 *)buf)); cur_value 2094 drivers/net/ethernet/qlogic/qed/qed_main.c nvm_image.start_addr + offset, cur_value, cur_value 2095 drivers/net/ethernet/qlogic/qed/qed_main.c (cur_value & ~mask) | (value & mask), value, mask); cur_value 2096 drivers/net/ethernet/qlogic/qed/qed_main.c value = (value & mask) | (cur_value & ~mask); cur_value 35 drivers/power/supply/s3c_adc_battery.c int cur_value; cur_value 159 drivers/power/supply/s3c_adc_battery.c if (bat->volt_value < 0 || bat->cur_value < 0 || cur_value 165 drivers/power/supply/s3c_adc_battery.c bat->cur_value = gather_samples(bat->client, cur_value 180 drivers/power/supply/s3c_adc_battery.c (bat->cur_value / 1000), bat->pdata->internal_impedance); cur_value 228 drivers/power/supply/s3c_adc_battery.c val->intval = bat->cur_value; cur_value 310 drivers/power/supply/s3c_adc_battery.c main_bat.cur_value = -1; cur_value 930 drivers/scsi/bfa/bfa_defs_svc.h u16 cur_value; cur_value 3895 drivers/scsi/bfa/bfa_fcpim.c throttle.cur_value = (u16)(fcpim->fcp->num_ioim_reqs); cur_value 3898 drivers/scsi/bfa/bfa_fcpim.c throttle.cfg_value = throttle.cur_value; cur_value 293 drivers/xen/xen-pciback/conf_space_header.c u8 cur_value; cur_value 296 drivers/xen/xen-pciback/conf_space_header.c err = pci_read_config_byte(dev, offset, &cur_value); cur_value 300 drivers/xen/xen-pciback/conf_space_header.c if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START) cur_value 155 sound/xen/xen_snd_front_cfg.c unsigned int cur_value; cur_value 170 sound/xen/xen_snd_front_cfg.c cur_value = CFG_HW_SUPPORTED_RATES[i].value; cur_value 172 sound/xen/xen_snd_front_cfg.c if (rate_min > cur_value) cur_value 173 sound/xen/xen_snd_front_cfg.c rate_min = cur_value; cur_value 174 sound/xen/xen_snd_front_cfg.c if (rate_max < cur_value) cur_value 175 sound/xen/xen_snd_front_cfg.c rate_max = cur_value;