cur_min_clks_state  263 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
cur_min_clks_state  409 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
cur_min_clks_state  410 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
cur_min_clks_state  412 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
cur_min_clks_state  461 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
cur_min_clks_state  262 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
cur_min_clks_state  263 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
cur_min_clks_state  265 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
cur_min_clks_state   98 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
cur_min_clks_state  152 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
cur_min_clks_state  207 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
cur_min_clks_state  208 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
cur_min_clks_state  210 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
cur_min_clks_state  280 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
cur_min_clks_state  314 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
cur_min_clks_state  682 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
cur_min_clks_state  683 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
cur_min_clks_state  685 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
cur_min_clks_state  709 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
cur_min_clks_state  710 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
cur_min_clks_state  712 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
cur_min_clks_state  736 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
cur_min_clks_state  737 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
cur_min_clks_state  739 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
cur_min_clks_state  835 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
cur_min_clks_state  261 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 	enum dm_pp_clocks_state cur_min_clks_state;