DF_BASE            43 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
DF_BASE            43 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
DF_BASE            43 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
DF_BASE            43 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
DF_BASE            45 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
DF_BASE            44 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
DF_BASE            55 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } },
DF_BASE            49 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },
DF_BASE            53 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
DF_BASE            53 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
DF_BASE            67 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
DF_BASE            73 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DF_BASE			= { { { { 0x00007000, 0, 0, 0, 0 } },
DF_BASE            57 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },