ctx_sseu           33 drivers/gpu/drm/i915/gt/intel_sseu.c 	struct intel_sseu ctx_sseu;
ctx_sseu           53 drivers/gpu/drm/i915/gt/intel_sseu.c 		ctx_sseu = *req_sseu;
ctx_sseu           55 drivers/gpu/drm/i915/gt/intel_sseu.c 		ctx_sseu = intel_sseu_from_device_info(sseu);
ctx_sseu           63 drivers/gpu/drm/i915/gt/intel_sseu.c 			ctx_sseu.subslice_mask =
ctx_sseu           64 drivers/gpu/drm/i915/gt/intel_sseu.c 				~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2));
ctx_sseu           65 drivers/gpu/drm/i915/gt/intel_sseu.c 			ctx_sseu.slice_mask = 0x1;
ctx_sseu           69 drivers/gpu/drm/i915/gt/intel_sseu.c 	slices = hweight8(ctx_sseu.slice_mask);
ctx_sseu           70 drivers/gpu/drm/i915/gt/intel_sseu.c 	subslices = hweight8(ctx_sseu.subslice_mask);
ctx_sseu          143 drivers/gpu/drm/i915/gt/intel_sseu.c 		val = ctx_sseu.min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
ctx_sseu          149 drivers/gpu/drm/i915/gt/intel_sseu.c 		val = ctx_sseu.max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;