ctx_obj          3293 drivers/gpu/drm/i915/gt/intel_lrc.c 		    struct drm_i915_gem_object *ctx_obj,
ctx_obj          3301 drivers/gpu/drm/i915/gt/intel_lrc.c 	vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
ctx_obj          3340 drivers/gpu/drm/i915/gt/intel_lrc.c 	__i915_gem_object_flush_map(ctx_obj,
ctx_obj          3343 drivers/gpu/drm/i915/gt/intel_lrc.c 	i915_gem_object_unpin_map(ctx_obj);
ctx_obj          3350 drivers/gpu/drm/i915/gt/intel_lrc.c 	struct drm_i915_gem_object *ctx_obj;
ctx_obj          3367 drivers/gpu/drm/i915/gt/intel_lrc.c 	ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
ctx_obj          3368 drivers/gpu/drm/i915/gt/intel_lrc.c 	if (IS_ERR(ctx_obj))
ctx_obj          3369 drivers/gpu/drm/i915/gt/intel_lrc.c 		return PTR_ERR(ctx_obj);
ctx_obj          3371 drivers/gpu/drm/i915/gt/intel_lrc.c 	vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
ctx_obj          3395 drivers/gpu/drm/i915/gt/intel_lrc.c 	ret = populate_lr_context(ce, ctx_obj, engine, ring);
ctx_obj          3409 drivers/gpu/drm/i915/gt/intel_lrc.c 	i915_gem_object_put(ctx_obj);
ctx_obj            60 drivers/gpu/drm/i915/gvt/scheduler.c 	struct drm_i915_gem_object *ctx_obj =
ctx_obj            71 drivers/gpu/drm/i915/gvt/scheduler.c 	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
ctx_obj           131 drivers/gpu/drm/i915/gvt/scheduler.c 	struct drm_i915_gem_object *ctx_obj =
ctx_obj           139 drivers/gpu/drm/i915/gvt/scheduler.c 	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
ctx_obj           197 drivers/gpu/drm/i915/gvt/scheduler.c 		page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
ctx_obj           803 drivers/gpu/drm/i915/gvt/scheduler.c 	struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
ctx_obj           851 drivers/gpu/drm/i915/gvt/scheduler.c 		page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
ctx_obj           862 drivers/gpu/drm/i915/gvt/scheduler.c 	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);