ctx_mask          181 drivers/crypto/qat/qat_common/adf_common_drv.h 		   unsigned int ctx_mask);
ctx_mask          183 drivers/crypto/qat/qat_common/adf_common_drv.h 		  unsigned int ctx_mask);
ctx_mask          187 drivers/crypto/qat/qat_common/adf_common_drv.h 			  unsigned char ae, unsigned int ctx_mask);
ctx_mask          198 drivers/crypto/qat/qat_common/adf_common_drv.h 		    unsigned char ae, unsigned int ctx_mask, unsigned int upc);
ctx_mask          210 drivers/crypto/qat/qat_common/adf_common_drv.h 		     unsigned char ae, unsigned char ctx_mask,
ctx_mask          214 drivers/crypto/qat/qat_common/adf_common_drv.h 			 unsigned char ae, unsigned char ctx_mask,
ctx_mask          218 drivers/crypto/qat/qat_common/adf_common_drv.h 			 unsigned char ae, unsigned char ctx_mask,
ctx_mask          222 drivers/crypto/qat/qat_common/adf_common_drv.h 		    unsigned char ae, unsigned char ctx_mask,
ctx_mask          113 drivers/crypto/qat/qat_common/qat_hal.c 			  unsigned char ae, unsigned int ctx_mask)
ctx_mask          115 drivers/crypto/qat/qat_common/qat_hal.c 	AE(handle, ae).live_ctx_mask = ctx_mask;
ctx_mask          326 drivers/crypto/qat/qat_common/qat_hal.c 				unsigned char ae, unsigned int ctx_mask,
ctx_mask          334 drivers/crypto/qat/qat_common/qat_hal.c 		if (!(ctx_mask & (1 << ctx)))
ctx_mask          358 drivers/crypto/qat/qat_common/qat_hal.c 				  unsigned char ae, unsigned int ctx_mask,
ctx_mask          365 drivers/crypto/qat/qat_common/qat_hal.c 		if (!(ctx_mask & (1 << ctx)))
ctx_mask          374 drivers/crypto/qat/qat_common/qat_hal.c 				     unsigned char ae, unsigned int ctx_mask,
ctx_mask          381 drivers/crypto/qat/qat_common/qat_hal.c 		if (!(ctx_mask & (1 << ctx)))
ctx_mask          539 drivers/crypto/qat/qat_common/qat_hal.c 				unsigned char ae, unsigned int ctx_mask)
ctx_mask          545 drivers/crypto/qat/qat_common/qat_hal.c 		(~((ctx_mask & ICP_QAT_UCLO_AE_ALL_CTX) << CE_ENABLE_BITPOS));
ctx_mask          603 drivers/crypto/qat/qat_common/qat_hal.c 			       unsigned char ae, unsigned int ctx_mask)
ctx_mask          609 drivers/crypto/qat/qat_common/qat_hal.c 	ctx_mask &= (ctx & CE_INUSE_CONTEXTS) ? 0x55 : 0xFF;
ctx_mask          610 drivers/crypto/qat/qat_common/qat_hal.c 	ctx |= (ctx_mask << CE_ENABLE_BITPOS);
ctx_mask          632 drivers/crypto/qat/qat_common/qat_hal.c 	unsigned int ctx_mask = ICP_QAT_UCLO_AE_ALL_CTX;
ctx_mask          648 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,
ctx_mask          653 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_put_wakeup_event(handle, ae, ctx_mask, XCWE_VOLUNTARY);
ctx_mask          654 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_wr_indr_csr(handle, ae, ctx_mask,
ctx_mask          657 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_enable_ctx(handle, ae, ctx_mask);
ctx_mask          669 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_disable_ctx(handle, ae, ctx_mask);
ctx_mask          674 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,
ctx_mask          679 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_put_wakeup_event(handle, ae, ctx_mask,
ctx_mask          681 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_put_sig_event(handle, ae, ctx_mask,
ctx_mask          786 drivers/crypto/qat/qat_common/qat_hal.c 		   unsigned int ctx_mask)
ctx_mask          802 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_put_wakeup_event(handle, ae, (~ctx_mask) &
ctx_mask          804 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_enable_ctx(handle, ae, ctx_mask);
ctx_mask          809 drivers/crypto/qat/qat_common/qat_hal.c 		  unsigned int ctx_mask)
ctx_mask          812 drivers/crypto/qat/qat_common/qat_hal.c 		qat_hal_disable_ctx(handle, ae, ctx_mask);
ctx_mask          816 drivers/crypto/qat/qat_common/qat_hal.c 		    unsigned char ae, unsigned int ctx_mask, unsigned int upc)
ctx_mask          818 drivers/crypto/qat/qat_common/qat_hal.c 	qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,
ctx_mask         1317 drivers/crypto/qat/qat_common/qat_hal.c 		     unsigned char ae, unsigned char ctx_mask,
ctx_mask         1330 drivers/crypto/qat/qat_common/qat_hal.c 		if (ctx_mask == 0) {
ctx_mask         1337 drivers/crypto/qat/qat_common/qat_hal.c 			if (!test_bit(ctx, (unsigned long *)&ctx_mask))
ctx_mask         1345 drivers/crypto/qat/qat_common/qat_hal.c 	} while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX));
ctx_mask         1351 drivers/crypto/qat/qat_common/qat_hal.c 			 unsigned char ae, unsigned char ctx_mask,
ctx_mask         1364 drivers/crypto/qat/qat_common/qat_hal.c 		if (ctx_mask == 0) {
ctx_mask         1371 drivers/crypto/qat/qat_common/qat_hal.c 			if (!test_bit(ctx, (unsigned long *)&ctx_mask))
ctx_mask         1380 drivers/crypto/qat/qat_common/qat_hal.c 	} while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX));
ctx_mask         1386 drivers/crypto/qat/qat_common/qat_hal.c 			 unsigned char ae, unsigned char ctx_mask,
ctx_mask         1399 drivers/crypto/qat/qat_common/qat_hal.c 		if (ctx_mask == 0) {
ctx_mask         1406 drivers/crypto/qat/qat_common/qat_hal.c 			if (!test_bit(ctx, (unsigned long *)&ctx_mask))
ctx_mask         1415 drivers/crypto/qat/qat_common/qat_hal.c 	} while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX));
ctx_mask         1421 drivers/crypto/qat/qat_common/qat_hal.c 		    unsigned char ae, unsigned char ctx_mask,
ctx_mask         1427 drivers/crypto/qat/qat_common/qat_hal.c 	if (ctx_mask == 0)
ctx_mask         1431 drivers/crypto/qat/qat_common/qat_hal.c 		if (!test_bit(ctx, (unsigned long *)&ctx_mask))
ctx_mask          786 drivers/crypto/qat/qat_common/qat_uclo.c 			     unsigned char ae, unsigned char ctx_mask,
ctx_mask          793 drivers/crypto/qat/qat_common/qat_uclo.c 		ctx_mask = 0;
ctx_mask          797 drivers/crypto/qat/qat_common/qat_uclo.c 		return qat_hal_init_gpr(handle, ae, ctx_mask, reg_type,
ctx_mask          803 drivers/crypto/qat/qat_common/qat_uclo.c 		ctx_mask = 0;
ctx_mask          809 drivers/crypto/qat/qat_common/qat_uclo.c 		return qat_hal_init_rd_xfer(handle, ae, ctx_mask, reg_type,
ctx_mask          813 drivers/crypto/qat/qat_common/qat_uclo.c 		ctx_mask = 0;
ctx_mask          817 drivers/crypto/qat/qat_common/qat_uclo.c 		return qat_hal_init_wr_xfer(handle, ae, ctx_mask, reg_type,
ctx_mask          820 drivers/crypto/qat/qat_common/qat_uclo.c 		return qat_hal_init_nn(handle, ae, ctx_mask, reg_addr, value);
ctx_mask          833 drivers/crypto/qat/qat_common/qat_uclo.c 	unsigned char ctx_mask;
ctx_mask          838 drivers/crypto/qat/qat_common/qat_uclo.c 		ctx_mask = 0xff;
ctx_mask          840 drivers/crypto/qat/qat_common/qat_uclo.c 		ctx_mask = 0x55;
ctx_mask          849 drivers/crypto/qat/qat_common/qat_uclo.c 			qat_uclo_init_reg(handle, ae, ctx_mask,
ctx_mask          857 drivers/crypto/qat/qat_common/qat_uclo.c 			if (!((1 << init_regsym->ctx) & ctx_mask)) {
ctx_mask         1587 drivers/crypto/qat/qat_common/qat_uclo.c 	unsigned int ctx_mask, s;
ctx_mask         1593 drivers/crypto/qat/qat_common/qat_uclo.c 		ctx_mask = 0xff;
ctx_mask         1595 drivers/crypto/qat/qat_common/qat_uclo.c 		ctx_mask = 0x55;
ctx_mask         1617 drivers/crypto/qat/qat_common/qat_uclo.c 					(ctx_mask & (1 << ctx)) ? page : NULL;
ctx_mask          125 drivers/net/ethernet/marvell/octeontx2/af/common.h 	struct	npa_aura_s	ctx_mask;
ctx_mask          132 drivers/net/ethernet/marvell/octeontx2/af/common.h 	struct	npa_pool_s	ctx_mask;