ctx_desc          467 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);
ctx_desc          470 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 	guc_wq_item_append(client, engine->guc_id, ctx_desc,
ctx_desc          421 drivers/gpu/drm/i915/gvt/execlist.c 		this_desc = &workload->ctx_desc;
ctx_desc          422 drivers/gpu/drm/i915/gvt/execlist.c 		next_desc = &next_workload->ctx_desc;
ctx_desc          432 drivers/gpu/drm/i915/gvt/execlist.c 	ret = emulate_execlist_ctx_schedule_out(execlist, &workload->ctx_desc);
ctx_desc          178 drivers/gpu/drm/i915/gvt/scheduler.c 			workload->ctx_desc.lrca);
ctx_desc          190 drivers/gpu/drm/i915/gvt/scheduler.c 				(u32)((workload->ctx_desc.lrca + i) <<
ctx_desc          295 drivers/gpu/drm/i915/gvt/scheduler.c 	desc |= workload->ctx_desc.addressing_mode <<
ctx_desc          815 drivers/gpu/drm/i915/gvt/scheduler.c 		      workload->ctx_desc.lrca);
ctx_desc          844 drivers/gpu/drm/i915/gvt/scheduler.c 				(u32)((workload->ctx_desc.lrca + i) <<
ctx_desc         1431 drivers/gpu/drm/i915/gvt/scheduler.c 	struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
ctx_desc         1509 drivers/gpu/drm/i915/gvt/scheduler.c 		if (same_context(&last_workload->ctx_desc, desc)) {
ctx_desc         1544 drivers/gpu/drm/i915/gvt/scheduler.c 	workload->ctx_desc = *desc;
ctx_desc          100 drivers/gpu/drm/i915/gvt/scheduler.h 	struct execlist_ctx_descriptor_format ctx_desc;