ctx0              193 drivers/gpu/drm/i915/gvt/execlist.c 	struct execlist_ctx_descriptor_format *ctx0 = &running->ctx[0];
ctx0              210 drivers/gpu/drm/i915/gvt/execlist.c 	if (valid_context(ctx1) && same_context(ctx0, ctx)) {
ctx0              229 drivers/gpu/drm/i915/gvt/execlist.c 	} else if ((!valid_context(ctx1) && same_context(ctx0, ctx))
ctx0              287 drivers/gpu/drm/i915/gvt/execlist.c 	struct execlist_ctx_descriptor_format *ctx0, *ctx1;
ctx0              332 drivers/gpu/drm/i915/gvt/execlist.c 	ctx0 = &running->ctx[0];
ctx0              336 drivers/gpu/drm/i915/gvt/execlist.c 		running->index, ctx0->context_id, ctx1->context_id);
ctx0              348 drivers/gpu/drm/i915/gvt/execlist.c 		(!same_context(ctx0, execlist->running_context))) ||
ctx0              350 drivers/gpu/drm/i915/gvt/execlist.c 			 same_context(ctx0, &slot->ctx[0]))) { /* condition b */
ctx0              495 drivers/infiniband/hw/cxgb3/cxio_hal.c 	u64 sge_cmd, ctx0, ctx1;
ctx0              531 drivers/infiniband/hw/cxgb3/cxio_hal.c 	ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
ctx0              533 drivers/infiniband/hw/cxgb3/cxio_hal.c 	ctx0 <<= 32;
ctx0              534 drivers/infiniband/hw/cxgb3/cxio_hal.c 	ctx0 |= V_EC_CREDITS(FW_WR_NUM);
ctx0              548 drivers/infiniband/hw/cxgb3/cxio_hal.c 	wqe->ctx0 = cpu_to_be64(ctx0);
ctx0              292 drivers/infiniband/hw/cxgb3/cxio_wr.h 	__be64 ctx0;		/* 6 */
ctx0              678 drivers/scsi/qla2xxx/qla_os.c 		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
ctx0              680 drivers/scsi/qla2xxx/qla_os.c 		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
ctx0              780 drivers/scsi/qla2xxx/qla_os.c 		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
ctx0              782 drivers/scsi/qla2xxx/qla_os.c 		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);