ctv_enc_mode      150 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 			.ctv_enc_mode = {
ctv_enc_mode      166 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 			.ctv_enc_mode = {
ctv_enc_mode      182 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 			.ctv_enc_mode = {
ctv_enc_mode      198 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 			.ctv_enc_mode = {
ctv_enc_mode      550 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 		&get_tv_norm(encoder)->ctv_enc_mode.mode;
ctv_enc_mode      234 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
ctv_enc_mode      310 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 						&tv_norm->ctv_enc_mode.mode;
ctv_enc_mode      354 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 		adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
ctv_enc_mode      520 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 						&tv_norm->ctv_enc_mode.mode;
ctv_enc_mode      531 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 			regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
ctv_enc_mode      109 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h 		} ctv_enc_mode;