ctrl_val0         230 arch/mips/netlogic/xlp/nlm_hal.c 	unsigned int pll_post_div, ctrl_val0, ctrl_val1, denom;
ctrl_val0         235 arch/mips/netlogic/xlp/nlm_hal.c 		ctrl_val0 = nlm_read_sys_reg(clockbase,
ctrl_val0         241 arch/mips/netlogic/xlp/nlm_hal.c 		ctrl_val0 = nlm_read_sys_reg(sysbase,
ctrl_val0         248 arch/mips/netlogic/xlp/nlm_hal.c 	switch ((ctrl_val0 >> 24) & 0x7) {
ctrl_val0         310 arch/mips/netlogic/xlp/nlm_hal.c 	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx;
ctrl_val0         350 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(clockbase,
ctrl_val0         356 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(clockbase,
ctrl_val0         362 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(clockbase,
ctrl_val0         368 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(clockbase,
ctrl_val0         379 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(sysbase,
ctrl_val0         385 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(sysbase,
ctrl_val0         391 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(sysbase,
ctrl_val0         397 arch/mips/netlogic/xlp/nlm_hal.c 			ctrl_val0 = nlm_read_sys_reg(sysbase,
ctrl_val0         405 arch/mips/netlogic/xlp/nlm_hal.c 	vco_post_div = (ctrl_val0 >> 5) & 0x7;
ctrl_val0         406 arch/mips/netlogic/xlp/nlm_hal.c 	pll_post_div = (ctrl_val0 >> 24) & 0x7;