ctrl_pol           44 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	uint32_t dsi_hsync_skew, vsync_period, vsync_len, ctrl_pol;
ctrl_pol           52 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	ctrl_pol = 0;
ctrl_pol           54 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 		ctrl_pol |= MDP4_DSI_CTRL_POLARITY_HSYNC_LOW;
ctrl_pol           56 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 		ctrl_pol |= MDP4_DSI_CTRL_POLARITY_VSYNC_LOW;
ctrl_pol           80 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol);
ctrl_pol           90 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
ctrl_pol          102 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	ctrl_pol = 0;
ctrl_pol          104 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 		ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW;
ctrl_pol          106 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 		ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW;
ctrl_pol          134 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol);
ctrl_pol          261 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	uint32_t lcdc_hsync_skew, vsync_period, vsync_len, ctrl_pol;
ctrl_pol          273 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	ctrl_pol = 0;
ctrl_pol          275 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 		ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW;
ctrl_pol          277 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 		ctrl_pol |= MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW;
ctrl_pol          305 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_CTRL_POLARITY, ctrl_pol);
ctrl_pol          102 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
ctrl_pol          112 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	ctrl_pol = 0;
ctrl_pol          117 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 			ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
ctrl_pol          119 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 			ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
ctrl_pol          180 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);