ctrl_offset       354 drivers/dma/xilinx/xilinx_dma.c 	u32 ctrl_offset;
ctrl_offset       457 drivers/dma/xilinx/xilinx_dma.c 	readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \
ctrl_offset       479 drivers/dma/xilinx/xilinx_dma.c 	return dma_read(chan, chan->ctrl_offset + reg);
ctrl_offset       485 drivers/dma/xilinx/xilinx_dma.c 	dma_write(chan, chan->ctrl_offset + reg, value);
ctrl_offset       523 drivers/dma/xilinx/xilinx_dma.c 	lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
ctrl_offset      2443 drivers/dma/xilinx/xilinx_dma.c 		chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
ctrl_offset      2467 drivers/dma/xilinx/xilinx_dma.c 		chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
ctrl_offset       618 drivers/net/ethernet/netronome/nfp/nfp_net_common.c nfp_net_aux_irq_request(struct nfp_net *nn, u32 ctrl_offset,
ctrl_offset       634 drivers/net/ethernet/netronome/nfp/nfp_net_common.c 	nn_writeb(nn, ctrl_offset, entry->entry);
ctrl_offset       646 drivers/net/ethernet/netronome/nfp/nfp_net_common.c static void nfp_net_aux_irq_free(struct nfp_net *nn, u32 ctrl_offset,
ctrl_offset       649 drivers/net/ethernet/netronome/nfp/nfp_net_common.c 	nn_writeb(nn, ctrl_offset, 0xff);
ctrl_offset       383 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c static bool _dma64_addrext(struct dma_info *di, uint ctrl_offset)
ctrl_offset       386 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c 	bcma_set32(di->core, ctrl_offset, D64_XC_AE);
ctrl_offset       387 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c 	w = bcma_read32(di->core, ctrl_offset);
ctrl_offset       388 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c 	bcma_mask32(di->core, ctrl_offset, ~D64_XC_AE);
ctrl_offset       294 drivers/pinctrl/mediatek/mtk-eint.c 	unsigned int rst, ctrl_offset;
ctrl_offset       297 drivers/pinctrl/mediatek/mtk-eint.c 	ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
ctrl_offset       298 drivers/pinctrl/mediatek/mtk-eint.c 	dbnc = readl(eint->base + ctrl_offset);
ctrl_offset       301 drivers/pinctrl/mediatek/mtk-eint.c 		ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
ctrl_offset       303 drivers/pinctrl/mediatek/mtk-eint.c 		writel(rst, eint->base + ctrl_offset);
ctrl_offset       601 drivers/pinctrl/sirf/pinctrl-sirf.c 					  unsigned ctrl_offset)
ctrl_offset       605 drivers/pinctrl/sirf/pinctrl-sirf.c 	val = readl(sgpio->chip.regs + ctrl_offset);
ctrl_offset       607 drivers/pinctrl/sirf/pinctrl-sirf.c 	writel(val, sgpio->chip.regs + ctrl_offset);
ctrl_offset        71 drivers/reset/reset-lpc18xx.c 	u32 ctrl_offset = LPC18XX_RGU_CTRL0;
ctrl_offset        76 drivers/reset/reset-lpc18xx.c 	ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
ctrl_offset        82 drivers/reset/reset-lpc18xx.c 		writel(stat | rst_bit, rc->base + ctrl_offset);
ctrl_offset        84 drivers/reset/reset-lpc18xx.c 		writel(stat & ~rst_bit, rc->base + ctrl_offset);