DENORM_CONTROL    744 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);
DENORM_CONTROL     70 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DENORM_CONTROL, DCP, id), \
DENORM_CONTROL    128 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
DENORM_CONTROL    418 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t DENORM_CONTROL;
DENORM_CONTROL    105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_UPDATE(DENORM_CONTROL[opp_id],
DENORM_CONTROL    116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_UPDATE_2(DENORM_CONTROL[opp_id],
DENORM_CONTROL     79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	SRII(DENORM_CONTROL, MPC_OUT, inst),\
DENORM_CONTROL    126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t DENORM_CONTROL[MAX_OPP]; \