ctrl1 26 arch/mips/include/asm/sgi/ioc.h volatile u8 ctrl1; ctrl1 171 arch/mips/include/asm/txx9/tx4939.h __u32 ctrl1; ctrl1 368 drivers/crypto/bcm/spu2.c static void spu2_dump_fmd_ctrl1(u64 ctrl1) ctrl1 378 drivers/crypto/bcm/spu2.c packet_log(" FMD CTRL1 %#16llx\n", ctrl1); ctrl1 379 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_TAG_LOC) ctrl1 383 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_HAS_FR_DATA) ctrl1 385 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_HAS_AAD1) ctrl1 387 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_HAS_NAAD) ctrl1 389 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_HAS_AAD2) ctrl1 391 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_HAS_ESN) ctrl1 395 drivers/crypto/bcm/spu2.c hash_key_len = (ctrl1 & SPU2_HASH_KEY_LEN) >> SPU2_HASH_KEY_LEN_SHIFT; ctrl1 398 drivers/crypto/bcm/spu2.c ciph_key_len = (ctrl1 & SPU2_CIPH_KEY_LEN) >> SPU2_CIPH_KEY_LEN_SHIFT; ctrl1 401 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_GENIV) ctrl1 404 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_HASH_IV) ctrl1 407 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_RET_IV) ctrl1 410 drivers/crypto/bcm/spu2.c ret_iv_len = (ctrl1 & SPU2_RET_IV_LEN) >> SPU2_RET_IV_LEN_SHIFT; ctrl1 414 drivers/crypto/bcm/spu2.c iv_offset = (ctrl1 & SPU2_IV_OFFSET) >> SPU2_IV_OFFSET_SHIFT; ctrl1 417 drivers/crypto/bcm/spu2.c iv_len = (ctrl1 & SPU2_IV_LEN) >> SPU2_IV_LEN_SHIFT; ctrl1 420 drivers/crypto/bcm/spu2.c hash_tag_len = (ctrl1 & SPU2_HASH_TAG_LEN) >> SPU2_HASH_TAG_LEN_SHIFT; ctrl1 424 drivers/crypto/bcm/spu2.c ret_md = (ctrl1 & SPU2_RETURN_MD) >> SPU2_RETURN_MD_SHIFT; ctrl1 431 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_RETURN_FD) ctrl1 433 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_RETURN_AAD1) ctrl1 435 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_RETURN_NAAD) ctrl1 437 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_RETURN_AAD2) ctrl1 439 drivers/crypto/bcm/spu2.c if (ctrl1 & SPU2_RETURN_PAY) ctrl1 471 drivers/crypto/bcm/spu2.c spu2_dump_fmd_ctrl1(le64_to_cpu(fmd->ctrl1)); ctrl1 512 drivers/crypto/bcm/spu2.c u64 ctrl1; ctrl1 525 drivers/crypto/bcm/spu2.c ctrl1 = le64_to_cpu(fmd->ctrl1); ctrl1 526 drivers/crypto/bcm/spu2.c hash_key_len = (ctrl1 & SPU2_HASH_KEY_LEN) >> SPU2_HASH_KEY_LEN_SHIFT; ctrl1 527 drivers/crypto/bcm/spu2.c ciph_key_len = (ctrl1 & SPU2_CIPH_KEY_LEN) >> SPU2_CIPH_KEY_LEN_SHIFT; ctrl1 529 drivers/crypto/bcm/spu2.c ciph_iv_len = (ctrl1 & SPU2_IV_LEN) >> SPU2_IV_LEN_SHIFT; ctrl1 559 drivers/crypto/bcm/spu2.c u64 ctrl1; ctrl1 570 drivers/crypto/bcm/spu2.c ctrl1 = (cipher_key_len << SPU2_CIPH_KEY_LEN_SHIFT) | ctrl1 589 drivers/crypto/bcm/spu2.c fmd->ctrl1 = cpu_to_le64(ctrl1); ctrl1 667 drivers/crypto/bcm/spu2.c u64 ctrl1 = 0; ctrl1 670 drivers/crypto/bcm/spu2.c ctrl1 |= SPU2_TAG_LOC; ctrl1 673 drivers/crypto/bcm/spu2.c ctrl1 |= SPU2_HAS_AAD2; ctrl1 674 drivers/crypto/bcm/spu2.c ctrl1 |= SPU2_RETURN_AAD2; /* need aad2 for gcm aes esp */ ctrl1 678 drivers/crypto/bcm/spu2.c ctrl1 |= ((auth_key_len << SPU2_HASH_KEY_LEN_SHIFT) & ctrl1 682 drivers/crypto/bcm/spu2.c ctrl1 |= ((cipher_key_len << SPU2_CIPH_KEY_LEN_SHIFT) & ctrl1 686 drivers/crypto/bcm/spu2.c ctrl1 |= SPU2_GENIV; ctrl1 689 drivers/crypto/bcm/spu2.c ctrl1 |= SPU2_HASH_IV; ctrl1 692 drivers/crypto/bcm/spu2.c ctrl1 |= SPU2_RET_IV; ctrl1 693 drivers/crypto/bcm/spu2.c ctrl1 |= ret_iv_len << SPU2_RET_IV_LEN_SHIFT; ctrl1 694 drivers/crypto/bcm/spu2.c ctrl1 |= ret_iv_offset << SPU2_IV_OFFSET_SHIFT; ctrl1 697 drivers/crypto/bcm/spu2.c ctrl1 |= ((cipher_iv_len << SPU2_IV_LEN_SHIFT) & SPU2_IV_LEN); ctrl1 700 drivers/crypto/bcm/spu2.c ctrl1 |= ((digest_size << SPU2_HASH_TAG_LEN_SHIFT) & ctrl1 707 drivers/crypto/bcm/spu2.c ctrl1 |= ((u64)SPU2_RET_FMD_ONLY << SPU2_RETURN_MD_SHIFT); ctrl1 709 drivers/crypto/bcm/spu2.c ctrl1 |= ((u64)SPU2_RET_NO_MD << SPU2_RETURN_MD_SHIFT); ctrl1 714 drivers/crypto/bcm/spu2.c ctrl1 |= SPU2_RETURN_PAY; ctrl1 716 drivers/crypto/bcm/spu2.c fmd->ctrl1 = cpu_to_le64(ctrl1); ctrl1 77 drivers/crypto/bcm/spu2.h u64 ctrl1; ctrl1 463 drivers/crypto/chelsio/chcr_ipsec.c cpl->ctrl1 = cpu_to_be64(cntrl); ctrl1 197 drivers/extcon/extcon-max14577.c u8 ctrl1, ctrl2 = 0; ctrl1 210 drivers/extcon/extcon-max14577.c ctrl1 = val; ctrl1 212 drivers/extcon/extcon-max14577.c ctrl1 = CTRL1_SW_OPEN; ctrl1 216 drivers/extcon/extcon-max14577.c CLEAR_IDBEN_MICEN_MASK, ctrl1); ctrl1 237 drivers/extcon/extcon-max14577.c ctrl1, ctrl2, attached ? "attached" : "detached"); ctrl1 260 drivers/extcon/extcon-max77693.c unsigned int ctrl1, ctrl2 = 0; ctrl1 263 drivers/extcon/extcon-max77693.c ctrl1 = val; ctrl1 265 drivers/extcon/extcon-max77693.c ctrl1 = MAX77693_CONTROL1_SW_OPEN; ctrl1 268 drivers/extcon/extcon-max77693.c MAX77693_MUIC_REG_CTRL1, COMP_SW_MASK, ctrl1); ctrl1 290 drivers/extcon/extcon-max77693.c ctrl1, ctrl2, attached ? "attached" : "detached"); ctrl1 204 drivers/extcon/extcon-max77843.c unsigned int ctrl1, ctrl2; ctrl1 207 drivers/extcon/extcon-max77843.c ctrl1 = val; ctrl1 209 drivers/extcon/extcon-max77843.c ctrl1 = MAX77843_MUIC_CONTROL1_SW_OPEN; ctrl1 212 drivers/extcon/extcon-max77843.c ctrl1 |= MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK; ctrl1 219 drivers/extcon/extcon-max77843.c ctrl1); ctrl1 241 drivers/extcon/extcon-max77843.c ctrl1, ctrl2, attached ? "attached" : "detached"); ctrl1 198 drivers/extcon/extcon-max8997.c u8 ctrl1, ctrl2 = 0; ctrl1 201 drivers/extcon/extcon-max8997.c ctrl1 = val; ctrl1 203 drivers/extcon/extcon-max8997.c ctrl1 = CONTROL1_SW_OPEN; ctrl1 206 drivers/extcon/extcon-max8997.c MAX8997_MUIC_REG_CONTROL1, ctrl1, COMP_SW_MASK); ctrl1 227 drivers/extcon/extcon-max8997.c ctrl1, ctrl2, attached ? "attached" : "detached"); ctrl1 31 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl1; ctrl1 33 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 = readl(priv->base + CRT_CTRL1); ctrl1 34 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 &= ~CRT_CTRL_COLOR_MASK; ctrl1 39 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 |= CRT_CTRL_COLOR_RGB565; ctrl1 44 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 |= CRT_CTRL_COLOR_XRGB8888; ctrl1 52 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1, priv->base + CRT_CTRL1); ctrl1 59 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl1 = readl(priv->base + CRT_CTRL1); ctrl1 65 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1 | CRT_CTRL_EN, priv->base + CRT_CTRL1); ctrl1 71 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl1 = readl(priv->base + CRT_CTRL1); ctrl1 74 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1 & ~CRT_CTRL_EN, priv->base + CRT_CTRL1); ctrl1 83 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 ctrl1, d_offset, t_count, bpp; ctrl1 96 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 = readl(priv->base + CRT_CTRL1); ctrl1 97 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 &= ~(CRT_CTRL_INTERLACED | ctrl1 102 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 |= CRT_CTRL_INTERLACED; ctrl1 105 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 |= CRT_CTRL_HSYNC_NEGATIVE; ctrl1 108 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c ctrl1 |= CRT_CTRL_VSYNC_NEGATIVE; ctrl1 110 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(ctrl1, priv->base + CRT_CTRL1); ctrl1 187 drivers/gpu/drm/bridge/analogix-anx78xx.c u8 ctrl1 = msg->request; ctrl1 200 drivers/gpu/drm/bridge/analogix-anx78xx.c ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT; ctrl1 217 drivers/gpu/drm/bridge/analogix-anx78xx.c ctrl1); ctrl1 1570 drivers/gpu/drm/i915/display/intel_ddi.c if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { ctrl1 1573 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); ctrl1 12801 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); ctrl1 995 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= pll->state.hw_state.ctrl1 << (id * 6); ctrl1 1067 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; ctrl1 1105 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; ctrl1 1363 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 ctrl1, cfgcr1, cfgcr2; ctrl1 1370 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 = DPLL_CTRL1_OVERRIDE(0); ctrl1 1372 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); ctrl1 1391 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.ctrl1 = ctrl1; ctrl1 1400 drivers/gpu/drm/i915/display/intel_dpll_mgr.c u32 ctrl1; ctrl1 1406 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 = DPLL_CTRL1_OVERRIDE(0); ctrl1 1409 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); ctrl1 1412 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); ctrl1 1415 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); ctrl1 1419 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0); ctrl1 1422 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0); ctrl1 1425 drivers/gpu/drm/i915/display/intel_dpll_mgr.c ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0); ctrl1 1432 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.ctrl1 = ctrl1; ctrl1 1488 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1, ctrl1 186 drivers/gpu/drm/i915/display/intel_dpll_mgr.h u32 ctrl1; ctrl1 204 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, ctrl1 212 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c gpu_write(gpu, ctrl1, i); ctrl1 51 drivers/gpu/drm/mxsfb/mxsfb_crtc.c u32 ctrl, ctrl1; ctrl1 63 drivers/gpu/drm/mxsfb/mxsfb_crtc.c ctrl1 = readl(mxsfb->base + LCDC_CTRL1); ctrl1 64 drivers/gpu/drm/mxsfb/mxsfb_crtc.c ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ; ctrl1 70 drivers/gpu/drm/mxsfb/mxsfb_crtc.c ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf); ctrl1 76 drivers/gpu/drm/mxsfb/mxsfb_crtc.c ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7); ctrl1 83 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(ctrl1, mxsfb->base + LCDC_CTRL1); ctrl1 132 drivers/gpu/drm/tve200/tve200_display.c u32 ctrl1 = 0; ctrl1 137 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_CSMODE; ctrl1 139 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_NONINTERLACE; ctrl1 141 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_BURST_32_WORDS; ctrl1 143 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_RETRYCNT_16; ctrl1 145 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_NTSC; ctrl1 148 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_VSTSTYPE_VSYNC; ctrl1 152 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_TVCLKP; ctrl1 156 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_IPRESOL_CIF; ctrl1 159 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_IPRESOL_VGA; ctrl1 163 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_IPRESOL_D1; ctrl1 168 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_BBBP; ctrl1 174 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_RGB888; ctrl1 177 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_RGB565; ctrl1 180 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_RGB555; ctrl1 183 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_RGB888 | TVE200_BGR; ctrl1 186 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_RGB565 | TVE200_BGR; ctrl1 189 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_RGB555 | TVE200_BGR; ctrl1 192 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_YUV422; ctrl1 193 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0; ctrl1 196 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_YUV422; ctrl1 197 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0; ctrl1 200 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_YUV422; ctrl1 201 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0; ctrl1 204 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_YUV422; ctrl1 205 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0; ctrl1 208 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_CTRL_YUV420; ctrl1 209 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_IPDMOD_YUV420; ctrl1 217 drivers/gpu/drm/tve200/tve200_display.c ctrl1 |= TVE200_TVEEN; ctrl1 220 drivers/gpu/drm/tve200/tve200_display.c writel(ctrl1, priv->regs + TVE200_CTRL); ctrl1 116 drivers/leds/leds-is31fl319x.c u8 ctrl1 = 0, ctrl2 = 0; ctrl1 143 drivers/leds/leds-is31fl319x.c ctrl1 |= on << i; /* 0..2 => bit 0..2 */ ctrl1 145 drivers/leds/leds-is31fl319x.c ctrl1 |= on << (i + 1); /* 3..5 => bit 4..6 */ ctrl1 150 drivers/leds/leds-is31fl319x.c if (ctrl1 > 0 || ctrl2 > 0) { ctrl1 152 drivers/leds/leds-is31fl319x.c ctrl1, ctrl2); ctrl1 153 drivers/leds/leds-is31fl319x.c regmap_write(is31->regmap, IS31FL319X_CTRL1, ctrl1); ctrl1 167 drivers/mailbox/bcm-pdc-mailbox.c u32 ctrl1; /* misc control bits */ ctrl1 532 drivers/mailbox/bcm-pdc-mailbox.c rxd->ctrl1 = cpu_to_le32(flags); ctrl1 560 drivers/mailbox/bcm-pdc-mailbox.c txd->ctrl1 = cpu_to_le32(flags); ctrl1 1058 drivers/mailbox/bcm-pdc-mailbox.c &pdcs->txd_64[i].ctrl1); ctrl1 1062 drivers/mailbox/bcm-pdc-mailbox.c D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1); ctrl1 1068 drivers/mailbox/bcm-pdc-mailbox.c &pdcs->rxd_64[i].ctrl1); ctrl1 1072 drivers/mailbox/bcm-pdc-mailbox.c &pdcs->rxd_64[i].ctrl1); ctrl1 205 drivers/media/i2c/ov2659.c u8 ctrl1; ctrl1 738 drivers/media/i2c/ov2659.c static const struct pll_ctrl_reg ctrl1[] = { ctrl1 921 drivers/media/i2c/ov2659.c for (i = 0; ctrl1[i].div != 0; i++) { ctrl1 922 drivers/media/i2c/ov2659.c postdiv = ctrl1[i].div; ctrl1 935 drivers/media/i2c/ov2659.c ctrl1_reg = ctrl1[i].reg; ctrl1 943 drivers/media/i2c/ov2659.c ov2659->pll.ctrl1 = ctrl1_reg; ctrl1 956 drivers/media/i2c/ov2659.c {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1}, ctrl1 88 drivers/mmc/host/mxs-mmc.c u32 ctrl0, ctrl1; ctrl1 96 drivers/mmc/host/mxs-mmc.c ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | ctrl1 113 drivers/mmc/host/mxs-mmc.c ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; ctrl1 117 drivers/mmc/host/mxs-mmc.c writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); ctrl1 148 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 152 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 159 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 180 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 188 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 269 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 399 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 420 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 437 drivers/net/can/cc770/cc770.c msgobj[mo].ctrl1) & TXRQST_UNC) == TXRQST_SET) { ctrl1 448 drivers/net/can/cc770/cc770.c static void cc770_rx(struct net_device *dev, unsigned int mo, u8 ctrl1) ctrl1 464 drivers/net/can/cc770/cc770.c if (ctrl1 & RMTPND_SET) { ctrl1 604 drivers/net/can/cc770/cc770.c u8 ctrl1; ctrl1 608 drivers/net/can/cc770/cc770.c ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1); ctrl1 610 drivers/net/can/cc770/cc770.c if (!(ctrl1 & NEWDAT_SET)) { ctrl1 621 drivers/net/can/cc770/cc770.c if (ctrl1 & MSGLST_SET) { ctrl1 626 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 629 drivers/net/can/cc770/cc770.c cc770_rx(dev, mo, ctrl1); ctrl1 634 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 644 drivers/net/can/cc770/cc770.c u8 ctrl0, ctrl1; ctrl1 652 drivers/net/can/cc770/cc770.c ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1); ctrl1 653 drivers/net/can/cc770/cc770.c cc770_rx(dev, mo, ctrl1); ctrl1 658 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 670 drivers/net/can/cc770/cc770.c u8 ctrl1; ctrl1 672 drivers/net/can/cc770/cc770.c ctrl1 = cc770_read_reg(priv, msgobj[mo].ctrl1); ctrl1 676 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl1, ctrl1 684 drivers/net/can/cc770/cc770.c if (unlikely(ctrl1 & MSGLST_SET)) { ctrl1 695 drivers/net/can/cc770/cc770.c if (unlikely(ctrl1 & NEWDAT_SET)) { ctrl1 696 drivers/net/can/cc770/cc770.c cc770_rx(dev, mo, ctrl1); ctrl1 15 drivers/net/can/cc770/cc770.h u8 ctrl1; ctrl1 1598 drivers/net/ethernet/chelsio/cxgb4/sge.c cpl->ctrl1 = cpu_to_be64(cntrl); ctrl1 1892 drivers/net/ethernet/chelsio/cxgb4/sge.c cpl->ctrl1 = cpu_to_be64(cntrl); ctrl1 822 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h __be64 ctrl1; ctrl1 1362 drivers/net/ethernet/chelsio/cxgb4vf/sge.c cpl->ctrl1 = cpu_to_be64(cntrl); ctrl1 474 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c u32 addr, val, ctrl1; ctrl1 489 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c ctrl1 = HINIC_AEQ_CTRL_1_SET(eq->q_len, LEN) | ctrl1 493 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl1; ctrl1 507 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c ctrl1 = HINIC_CEQ_CTRL_1_SET(eq->q_len, LEN) | ctrl1 510 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl1; ctrl1 1425 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14) ctrl1 1429 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32) ctrl1 1431 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16) ctrl1 17 drivers/net/phy/phy-c45.c int ctrl1, ctrl2, ret; ctrl1 23 drivers/net/phy/phy-c45.c ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); ctrl1 24 drivers/net/phy/phy-c45.c if (ctrl1 < 0) ctrl1 25 drivers/net/phy/phy-c45.c return ctrl1; ctrl1 31 drivers/net/phy/phy-c45.c ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; ctrl1 43 drivers/net/phy/phy-c45.c ctrl1 |= MDIO_PMA_CTRL1_SPEED100; ctrl1 47 drivers/net/phy/phy-c45.c ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; ctrl1 52 drivers/net/phy/phy-c45.c ctrl1 |= MDIO_CTRL1_SPEED2_5G; ctrl1 57 drivers/net/phy/phy-c45.c ctrl1 |= MDIO_CTRL1_SPEED5G; ctrl1 62 drivers/net/phy/phy-c45.c ctrl1 |= MDIO_CTRL1_SPEED10G; ctrl1 70 drivers/net/phy/phy-c45.c ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); ctrl1 360 drivers/net/wireless/ath/ath6kl/htc_mbox.c int ctrl0, int ctrl1) ctrl1 372 drivers/net/wireless/ath/ath6kl/htc_mbox.c hdr->ctrl[1] = ctrl1; ctrl1 146 drivers/net/wireless/ath/ath9k/ar9003_paprd.c static const u32 ctrl1[3] = { ctrl1 186 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl1[i], ctrl1 188 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl1[i], ctrl1 190 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl1[i], ctrl1 192 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl1[i], ctrl1 194 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl1[i], ctrl1 196 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl1[i], ctrl1 201 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c __le32 ctrl1; /* misc control bits & bufcount */ ctrl1 303 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c return parity32(dd->addrlow ^ dd->addrhigh ^ dd->ctrl1 ^ dd->ctrl2); ctrl1 724 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c ddring[outidx].ctrl1 = cpu_to_le32(*flags); ctrl1 736 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c ddring[outidx].ctrl1 = cpu_to_le32(*flags); ctrl1 724 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0, ctrl1; ctrl1 730 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); ctrl1 746 drivers/pinctrl/intel/pinctrl-cherryview.c seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); ctrl1 974 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0, ctrl1; ctrl1 980 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); ctrl1 1025 drivers/pinctrl/intel/pinctrl-cherryview.c if (!(ctrl1 & CHV_PADCTRL1_ODEN)) ctrl1 1119 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl1; ctrl1 1122 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl1 = readl(reg); ctrl1 1125 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl1 |= CHV_PADCTRL1_ODEN; ctrl1 1127 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl1 &= ~CHV_PADCTRL1_ODEN; ctrl1 1129 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl1, reg); ctrl1 275 drivers/regulator/tps80031-regulator.c uint8_t ctrl1 = 0; ctrl1 279 drivers/regulator/tps80031-regulator.c TPS80031_CHARGERUSB_CTRL1, &ctrl1); ctrl1 292 drivers/regulator/tps80031-regulator.c if ((ctrl1 & OPA_MODE_EN) && (ctrl3 & BOOST_HW_PWR_EN)) ctrl1 458 drivers/rtc/rtc-rv3028.c u32 status, ctrl1; ctrl1 462 drivers/rtc/rtc-rv3028.c ret = regmap_read(priv, RV3028_CTRL1, &ctrl1); ctrl1 466 drivers/rtc/rtc-rv3028.c if (!(ctrl1 & RV3028_CTRL1_EERD)) { ctrl1 509 drivers/rtc/rtc-rv3028.c if (!(ctrl1 & RV3028_CTRL1_EERD)) ctrl1 523 drivers/rtc/rtc-rv3028.c u32 status, ctrl1, data; ctrl1 527 drivers/rtc/rtc-rv3028.c ret = regmap_read(priv, RV3028_CTRL1, &ctrl1); ctrl1 531 drivers/rtc/rtc-rv3028.c if (!(ctrl1 & RV3028_CTRL1_EERD)) { ctrl1 573 drivers/rtc/rtc-rv3028.c if (!(ctrl1 & RV3028_CTRL1_EERD)) ctrl1 72 drivers/rtc/rtc-rx8025.c u8 ctrl1; ctrl1 168 drivers/rtc/rtc-rx8025.c rx8025->ctrl1 & ~RX8025_BIT_CTRL1_DALE)) ctrl1 197 drivers/rtc/rtc-rx8025.c if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) ctrl1 227 drivers/rtc/rtc-rx8025.c if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) ctrl1 259 drivers/rtc/rtc-rx8025.c rx8025->ctrl1 = ctrl[0] & ~RX8025_BIT_CTRL1_TEST; ctrl1 305 drivers/rtc/rtc-rx8025.c if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) ctrl1 312 drivers/rtc/rtc-rx8025.c t->enabled = !!(rx8025->ctrl1 & RX8025_BIT_CTRL1_DALE); ctrl1 340 drivers/rtc/rtc-rx8025.c if (rx8025->ctrl1 & RX8025_BIT_CTRL1_1224) ctrl1 348 drivers/rtc/rtc-rx8025.c if (rx8025->ctrl1 & RX8025_BIT_CTRL1_DALE) { ctrl1 349 drivers/rtc/rtc-rx8025.c rx8025->ctrl1 &= ~RX8025_BIT_CTRL1_DALE; ctrl1 351 drivers/rtc/rtc-rx8025.c rx8025->ctrl1); ctrl1 360 drivers/rtc/rtc-rx8025.c rx8025->ctrl1 |= RX8025_BIT_CTRL1_DALE; ctrl1 362 drivers/rtc/rtc-rx8025.c rx8025->ctrl1); ctrl1 373 drivers/rtc/rtc-rx8025.c u8 ctrl1; ctrl1 376 drivers/rtc/rtc-rx8025.c ctrl1 = rx8025->ctrl1; ctrl1 378 drivers/rtc/rtc-rx8025.c ctrl1 |= RX8025_BIT_CTRL1_DALE; ctrl1 380 drivers/rtc/rtc-rx8025.c ctrl1 &= ~RX8025_BIT_CTRL1_DALE; ctrl1 382 drivers/rtc/rtc-rx8025.c if (ctrl1 != rx8025->ctrl1) { ctrl1 383 drivers/rtc/rtc-rx8025.c rx8025->ctrl1 = ctrl1; ctrl1 385 drivers/rtc/rtc-rx8025.c rx8025->ctrl1); ctrl1 147 drivers/spi/spi-mpc52xx.c u8 ctrl1; ctrl1 162 drivers/spi/spi-mpc52xx.c ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; ctrl1 165 drivers/spi/spi-mpc52xx.c ctrl1 |= SPI_CTRL1_CPHA; ctrl1 167 drivers/spi/spi-mpc52xx.c ctrl1 |= SPI_CTRL1_CPOL; ctrl1 169 drivers/spi/spi-mpc52xx.c ctrl1 |= SPI_CTRL1_LSBFE; ctrl1 170 drivers/spi/spi-mpc52xx.c out_8(ms->regs + SPI_CTRL1, ctrl1); ctrl1 384 drivers/spi/spi-mpc52xx.c u8 ctrl1; ctrl1 395 drivers/spi/spi-mpc52xx.c ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; ctrl1 396 drivers/spi/spi-mpc52xx.c out_8(regs + SPI_CTRL1, ctrl1); ctrl1 406 drivers/spi/spi-mpc52xx.c out_8(regs + SPI_CTRL1, ctrl1); ctrl1 139 drivers/staging/comedi/drivers/me_daq.c unsigned short ctrl1; /* Mirror of CONTROL_1 register */ ctrl1 269 drivers/staging/comedi/drivers/me_daq.c devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG; ctrl1 270 drivers/staging/comedi/drivers/me_daq.c writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); ctrl1 289 drivers/staging/comedi/drivers/me_daq.c devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK; ctrl1 290 drivers/staging/comedi/drivers/me_daq.c writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); ctrl1 421 drivers/staging/comedi/drivers/me_daq.c devpriv->ctrl1 = 0; ctrl1 275 drivers/staging/ralink-gdma/ralink-gdma.c u32 ctrl0, ctrl1; ctrl1 318 drivers/staging/ralink-gdma/ralink-gdma.c ctrl1 = chan->id << GDMA_REG_CTRL1_NEXT_SHIFT; ctrl1 323 drivers/staging/ralink-gdma/ralink-gdma.c gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1); ctrl1 352 drivers/staging/ralink-gdma/ralink-gdma.c u32 ctrl0, ctrl1; ctrl1 368 drivers/staging/ralink-gdma/ralink-gdma.c ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | ctrl1 374 drivers/staging/ralink-gdma/ralink-gdma.c ctrl1 = (chan->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | ctrl1 381 drivers/staging/ralink-gdma/ralink-gdma.c ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) | ctrl1 393 drivers/staging/ralink-gdma/ralink-gdma.c ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT; ctrl1 398 drivers/staging/ralink-gdma/ralink-gdma.c gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1); ctrl1 503 drivers/thermal/armada_thermal.c u32 ctrl1; ctrl1 505 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, &ctrl1); ctrl1 509 drivers/thermal/armada_thermal.c ctrl1 &= ~(data->temp_mask << data->thresh_shift); ctrl1 510 drivers/thermal/armada_thermal.c ctrl1 |= threshold << data->thresh_shift; ctrl1 516 drivers/thermal/armada_thermal.c ctrl1 &= ~(data->hyst_mask << data->hyst_shift); ctrl1 517 drivers/thermal/armada_thermal.c ctrl1 |= hysteresis << data->hyst_shift; ctrl1 521 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, ctrl1); ctrl1 47 drivers/usb/cdns3/drd.c reg = readl(&cdns->otg_v0_regs->ctrl1); ctrl1 49 drivers/usb/cdns3/drd.c writel(reg, &cdns->otg_v0_regs->ctrl1); ctrl1 37 drivers/usb/cdns3/drd.h __le32 ctrl1; ctrl1 57 drivers/usb/cdns3/drd.h __le32 ctrl1; ctrl1 94 drivers/usb/host/sl811-hcd.c sl811->ctrl1 = 0; ctrl1 114 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 689 drivers/usb/host/sl811-hcd.c sl811->ctrl1 = 0; ctrl1 690 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 868 drivers/usb/host/sl811-hcd.c if (!(sl811->ctrl1 & SL11H_CTL1MASK_LSPD)) ctrl1 1127 drivers/usb/host/sl811-hcd.c u8 signaling = sl811->ctrl1 & SL11H_CTL1MASK_FORCE; ctrl1 1135 drivers/usb/host/sl811-hcd.c sl811->ctrl1 &= ~SL11H_CTL1MASK_FORCE; ctrl1 1136 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 1146 drivers/usb/host/sl811-hcd.c sl811->ctrl1 = 0; ctrl1 1184 drivers/usb/host/sl811-hcd.c sl811->ctrl1 |= SL11H_CTL1MASK_LSPD; ctrl1 1189 drivers/usb/host/sl811-hcd.c sl811->ctrl1 |= SL11H_CTL1MASK_SOF_ENA; ctrl1 1202 drivers/usb/host/sl811-hcd.c sl811->ctrl1 = 0; ctrl1 1204 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 1244 drivers/usb/host/sl811-hcd.c sl811->ctrl1 = 0; ctrl1 1245 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 1259 drivers/usb/host/sl811-hcd.c sl811->ctrl1 |= SL11H_CTL1MASK_K; ctrl1 1260 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 1307 drivers/usb/host/sl811-hcd.c sl811->ctrl1 &= ~SL11H_CTL1MASK_SOF_ENA; ctrl1 1308 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 1323 drivers/usb/host/sl811-hcd.c sl811->ctrl1 = SL11H_CTL1MASK_SE0; ctrl1 1324 drivers/usb/host/sl811-hcd.c sl811_write(sl811, SL11H_CTLREG1, sl811->ctrl1); ctrl1 1404 drivers/usb/host/sl811-hcd.c if (sl811->ctrl1 & SL11H_CTL1MASK_SUSPEND) ctrl1 147 drivers/usb/host/sl811.h u8 ctrl1, ctrl2, irq_enable; ctrl1 129 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define dma_ctrl(ctrl1, id) (ctrl1 ? dma_ctrl1(id) : dma_ctrl0(id)) ctrl1 1026 drivers/video/fbdev/mmp/hw/mmp_ctrl.h u32 ctrl1; ctrl1 1058 drivers/video/fbdev/mmp/hw/mmp_ctrl.h u32 ctrl1; ctrl1 891 sound/pci/oxygen/xonar_wm87x6.c u16 ctrl1, ctrl2; ctrl1 900 sound/pci/oxygen/xonar_wm87x6.c ctrl1 = data->wm8776_regs[WM8776_ALCCTRL1]; ctrl1 909 sound/pci/oxygen/xonar_wm87x6.c (ctrl1 & ~WM8776_LCSEL_MASK) | ctrl1 917 sound/pci/oxygen/xonar_wm87x6.c (ctrl1 & ~WM8776_LCSEL_MASK) | ctrl1 555 sound/soc/codecs/adau17x1.c unsigned int ctrl0, ctrl1; ctrl1 574 sound/soc/codecs/adau17x1.c ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; ctrl1 579 sound/soc/codecs/adau17x1.c ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; ctrl1 584 sound/soc/codecs/adau17x1.c ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; ctrl1 589 sound/soc/codecs/adau17x1.c ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; ctrl1 616 sound/soc/codecs/adau17x1.c regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1); ctrl1 301 sound/soc/codecs/adau1977.c unsigned int ctrl1; ctrl1 337 sound/soc/codecs/adau1977.c ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT; ctrl1 342 sound/soc/codecs/adau1977.c ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT; ctrl1 354 sound/soc/codecs/adau1977.c ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16; ctrl1 356 sound/soc/codecs/adau1977.c ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32; ctrl1 362 sound/soc/codecs/adau1977.c ctrl1); ctrl1 500 sound/soc/codecs/adau1977.c unsigned int ctrl0, ctrl1, drv; ctrl1 533 sound/soc/codecs/adau1977.c ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16; ctrl1 539 sound/soc/codecs/adau1977.c ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24; ctrl1 542 sound/soc/codecs/adau1977.c ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32; ctrl1 591 sound/soc/codecs/adau1977.c ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1); ctrl1 620 sound/soc/codecs/adau1977.c unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0; ctrl1 629 sound/soc/codecs/adau1977.c ctrl1 |= ADAU1977_SAI_CTRL1_MASTER; ctrl1 670 sound/soc/codecs/adau1977.c ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE; ctrl1 675 sound/soc/codecs/adau1977.c ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE; ctrl1 700 sound/soc/codecs/adau1977.c ctrl1); ctrl1 341 sound/soc/codecs/ssm2518.c unsigned int ctrl1, ctrl1_mask; ctrl1 352 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_FS_8000_12000; ctrl1 354 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_FS_16000_24000; ctrl1 356 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_FS_32000_48000; ctrl1 358 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_FS_64000_96000; ctrl1 365 sound/soc/codecs/ssm2518.c ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_16BIT; ctrl1 368 sound/soc/codecs/ssm2518.c ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT; ctrl1 383 sound/soc/codecs/ssm2518.c ctrl1_mask, ctrl1); ctrl1 408 sound/soc/codecs/ssm2518.c unsigned int ctrl1 = 0, ctrl2 = 0; ctrl1 441 sound/soc/codecs/ssm2518.c ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S; ctrl1 444 sound/soc/codecs/ssm2518.c ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ; ctrl1 448 sound/soc/codecs/ssm2518.c ctrl1 |= SSM2518_SAI_CTRL1_FMT_RJ_24BIT; ctrl1 454 sound/soc/codecs/ssm2518.c ctrl1 |= SSM2518_SAI_CTRL1_FMT_I2S; ctrl1 459 sound/soc/codecs/ssm2518.c ctrl1 |= SSM2518_SAI_CTRL1_FMT_LJ; ctrl1 469 sound/soc/codecs/ssm2518.c ret = regmap_write(ssm2518->regmap, SSM2518_REG_SAI_CTRL1, ctrl1); ctrl1 527 sound/soc/codecs/ssm2518.c unsigned int ctrl1, ctrl2; ctrl1 575 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_SAI_MONO; ctrl1 578 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_2; ctrl1 581 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_4; ctrl1 584 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_8; ctrl1 587 sound/soc/codecs/ssm2518.c ctrl1 = SSM2518_SAI_CTRL1_SAI_TDM_16; ctrl1 600 sound/soc/codecs/ssm2518.c SSM2518_SAI_CTRL1_SAI_MASK, ctrl1); ctrl1 278 sound/soc/codecs/ssm4567.c unsigned int ctrl1 = 0; ctrl1 293 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_BCLK; ctrl1 297 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_FSYNC; ctrl1 301 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_BCLK; ctrl1 312 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_LJ; ctrl1 316 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_TDM; ctrl1 319 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_TDM | SSM4567_SAI_CTRL_1_LJ; ctrl1 322 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_PDM; ctrl1 329 sound/soc/codecs/ssm4567.c ctrl1 |= SSM4567_SAI_CTRL_1_FSYNC; ctrl1 337 sound/soc/codecs/ssm4567.c ctrl1);