ctrl0 308 drivers/crypto/bcm/spu2.c static void spu2_dump_fmd_ctrl0(u64 ctrl0) ctrl0 321 drivers/crypto/bcm/spu2.c packet_log(" FMD CTRL0 %#16llx\n", ctrl0); ctrl0 322 drivers/crypto/bcm/spu2.c if (ctrl0 & SPU2_CIPH_ENCRYPT_EN) ctrl0 327 drivers/crypto/bcm/spu2.c ciph_type = (ctrl0 & SPU2_CIPH_TYPE) >> SPU2_CIPH_TYPE_SHIFT; ctrl0 332 drivers/crypto/bcm/spu2.c ciph_mode = (ctrl0 & SPU2_CIPH_MODE) >> SPU2_CIPH_MODE_SHIFT; ctrl0 337 drivers/crypto/bcm/spu2.c cfb = (ctrl0 & SPU2_CFB_MASK) >> SPU2_CFB_MASK_SHIFT; ctrl0 340 drivers/crypto/bcm/spu2.c proto = (ctrl0 & SPU2_PROTO_SEL) >> SPU2_PROTO_SEL_SHIFT; ctrl0 343 drivers/crypto/bcm/spu2.c if (ctrl0 & SPU2_HASH_FIRST) ctrl0 348 drivers/crypto/bcm/spu2.c if (ctrl0 & SPU2_CHK_TAG) ctrl0 351 drivers/crypto/bcm/spu2.c hash_type = (ctrl0 & SPU2_HASH_TYPE) >> SPU2_HASH_TYPE_SHIFT; ctrl0 356 drivers/crypto/bcm/spu2.c hash_mode = (ctrl0 & SPU2_HASH_MODE) >> SPU2_HASH_MODE_SHIFT; ctrl0 361 drivers/crypto/bcm/spu2.c if (ctrl0 & SPU2_CIPH_PAD_EN) { ctrl0 363 drivers/crypto/bcm/spu2.c (ctrl0 & SPU2_CIPH_PAD) >> SPU2_CIPH_PAD_SHIFT); ctrl0 470 drivers/crypto/bcm/spu2.c spu2_dump_fmd_ctrl0(le64_to_cpu(fmd->ctrl0)); ctrl0 558 drivers/crypto/bcm/spu2.c u64 ctrl0; ctrl0 567 drivers/crypto/bcm/spu2.c ctrl0 = (spu2_type << SPU2_CIPH_TYPE_SHIFT) | ctrl0 588 drivers/crypto/bcm/spu2.c fmd->ctrl0 = cpu_to_le64(ctrl0); ctrl0 616 drivers/crypto/bcm/spu2.c u64 ctrl0 = 0; ctrl0 619 drivers/crypto/bcm/spu2.c ctrl0 |= SPU2_CIPH_ENCRYPT_EN; ctrl0 621 drivers/crypto/bcm/spu2.c ctrl0 |= ((u64)cipher_type << SPU2_CIPH_TYPE_SHIFT) | ctrl0 625 drivers/crypto/bcm/spu2.c ctrl0 |= (u64)protocol << SPU2_PROTO_SEL_SHIFT; ctrl0 628 drivers/crypto/bcm/spu2.c ctrl0 |= SPU2_HASH_FIRST; ctrl0 631 drivers/crypto/bcm/spu2.c ctrl0 |= SPU2_CHK_TAG; ctrl0 633 drivers/crypto/bcm/spu2.c ctrl0 |= (((u64)auth_type << SPU2_HASH_TYPE_SHIFT) | ctrl0 636 drivers/crypto/bcm/spu2.c fmd->ctrl0 = cpu_to_le64(ctrl0); ctrl0 1192 drivers/crypto/bcm/spu2.c u64 ctrl0; ctrl0 1215 drivers/crypto/bcm/spu2.c ctrl0 = le64_to_cpu(fmd->ctrl0); ctrl0 1217 drivers/crypto/bcm/spu2.c ctrl0 &= ~SPU2_CIPH_ENCRYPT_EN; /* decrypt */ ctrl0 1219 drivers/crypto/bcm/spu2.c ctrl0 |= SPU2_CIPH_ENCRYPT_EN; /* encrypt */ ctrl0 1220 drivers/crypto/bcm/spu2.c fmd->ctrl0 = cpu_to_le64(ctrl0); ctrl0 76 drivers/crypto/bcm/spu2.h u64 ctrl0; ctrl0 437 drivers/crypto/chelsio/chcr_ipsec.c u32 ctrl0, qidx; ctrl0 453 drivers/crypto/chelsio/chcr_ipsec.c ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) | ctrl0 460 drivers/crypto/chelsio/chcr_ipsec.c cpl->ctrl0 = htonl(ctrl0); ctrl0 204 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, ctrl0 209 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c gpu_write(gpu, ctrl0, reg); ctrl0 115 drivers/input/rmi4/rmi_f01.c u8 ctrl0; ctrl0 411 drivers/input/rmi4/rmi_f01.c &f01->device_control.ctrl0); ctrl0 421 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_NOSLEEP_BIT; ctrl0 424 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT; ctrl0 433 drivers/input/rmi4/rmi_f01.c if ((f01->device_control.ctrl0 & RMI_F01_CTRL0_SLEEP_MODE_MASK) != ctrl0 437 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK; ctrl0 440 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_F01_CTRL0_CONFIGURED_BIT; ctrl0 443 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0); ctrl0 589 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0); ctrl0 636 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 & RMI_F01_CTRL0_NOSLEEP_BIT; ctrl0 637 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_NOSLEEP_BIT; ctrl0 639 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK; ctrl0 641 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_SLEEP_MODE_RESERVED1; ctrl0 643 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_SLEEP_MODE_SENSOR_SLEEP; ctrl0 646 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0); ctrl0 650 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT; ctrl0 651 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK; ctrl0 652 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_SLEEP_MODE_NORMAL; ctrl0 665 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_F01_CTRL0_NOSLEEP_BIT; ctrl0 667 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 &= ~RMI_F01_CTRL0_SLEEP_MODE_MASK; ctrl0 668 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0 |= RMI_SLEEP_MODE_NORMAL; ctrl0 671 drivers/input/rmi4/rmi_f01.c f01->device_control.ctrl0); ctrl0 40 drivers/media/platform/vsp1/vsp1_sru.c u32 ctrl0; ctrl0 55 drivers/media/platform/vsp1/vsp1_sru.c .ctrl0 = VI6_SRU_CTRL0_PARAMS(256, 4) | VI6_SRU_CTRL0_EN, ctrl0 58 drivers/media/platform/vsp1/vsp1_sru.c .ctrl0 = VI6_SRU_CTRL0_PARAMS(256, 4) | VI6_SRU_CTRL0_EN, ctrl0 61 drivers/media/platform/vsp1/vsp1_sru.c .ctrl0 = VI6_SRU_CTRL0_PARAMS(384, 5) | VI6_SRU_CTRL0_EN, ctrl0 64 drivers/media/platform/vsp1/vsp1_sru.c .ctrl0 = VI6_SRU_CTRL0_PARAMS(384, 5) | VI6_SRU_CTRL0_EN, ctrl0 67 drivers/media/platform/vsp1/vsp1_sru.c .ctrl0 = VI6_SRU_CTRL0_PARAMS(511, 6) | VI6_SRU_CTRL0_EN, ctrl0 70 drivers/media/platform/vsp1/vsp1_sru.c .ctrl0 = VI6_SRU_CTRL0_PARAMS(511, 6) | VI6_SRU_CTRL0_EN, ctrl0 279 drivers/media/platform/vsp1/vsp1_sru.c u32 ctrl0; ctrl0 287 drivers/media/platform/vsp1/vsp1_sru.c ctrl0 = VI6_SRU_CTRL0_PARAM2 | VI6_SRU_CTRL0_PARAM3 ctrl0 290 drivers/media/platform/vsp1/vsp1_sru.c ctrl0 = VI6_SRU_CTRL0_PARAM3; ctrl0 293 drivers/media/platform/vsp1/vsp1_sru.c ctrl0 |= VI6_SRU_CTRL0_MODE_UPSCALE; ctrl0 297 drivers/media/platform/vsp1/vsp1_sru.c ctrl0 |= param->ctrl0; ctrl0 299 drivers/media/platform/vsp1/vsp1_sru.c vsp1_sru_write(sru, dlb, VI6_SRU_CTRL0, ctrl0); ctrl0 88 drivers/mmc/host/mxs-mmc.c u32 ctrl0, ctrl1; ctrl0 95 drivers/mmc/host/mxs-mmc.c ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; ctrl0 112 drivers/mmc/host/mxs-mmc.c ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; ctrl0 116 drivers/mmc/host/mxs-mmc.c writel(ctrl0, ssp->base + HW_SSP_CTRL0); ctrl0 254 drivers/mmc/host/mxs-mmc.c u32 ctrl0, cmd0, cmd1; ctrl0 256 drivers/mmc/host/mxs-mmc.c ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; ctrl0 261 drivers/mmc/host/mxs-mmc.c ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; ctrl0 265 drivers/mmc/host/mxs-mmc.c ssp->ssp_pio_words[0] = ctrl0; ctrl0 289 drivers/mmc/host/mxs-mmc.c u32 ctrl0, cmd0, cmd1; ctrl0 298 drivers/mmc/host/mxs-mmc.c ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; ctrl0 306 drivers/mmc/host/mxs-mmc.c ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; ctrl0 310 drivers/mmc/host/mxs-mmc.c ssp->ssp_pio_words[0] = ctrl0; ctrl0 361 drivers/mmc/host/mxs-mmc.c u32 ctrl0, cmd0, cmd1, val; ctrl0 380 drivers/mmc/host/mxs-mmc.c ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | ctrl0 403 drivers/mmc/host/mxs-mmc.c ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); ctrl0 419 drivers/mmc/host/mxs-mmc.c ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; ctrl0 431 drivers/mmc/host/mxs-mmc.c ssp->ssp_pio_words[0] = ctrl0; ctrl0 143 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 162 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 183 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 191 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 263 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 266 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 397 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 422 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 613 drivers/net/can/cc770/cc770.c if (!(cc770_read_reg(priv, msgobj[mo].ctrl0) & ctrl0 631 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 644 drivers/net/can/cc770/cc770.c u8 ctrl0, ctrl1; ctrl0 648 drivers/net/can/cc770/cc770.c ctrl0 = cc770_read_reg(priv, msgobj[mo].ctrl0); ctrl0 649 drivers/net/can/cc770/cc770.c if (!(ctrl0 & INTPND_SET)) ctrl0 655 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 674 drivers/net/can/cc770/cc770.c cc770_write_reg(priv, msgobj[mo].ctrl0, ctrl0 14 drivers/net/can/cc770/cc770.h u8 ctrl0; ctrl0 1365 drivers/net/ethernet/chelsio/cxgb4/sge.c u32 wr_mid, ctrl0, op; ctrl0 1585 drivers/net/ethernet/chelsio/cxgb4/sge.c ctrl0 = TXPKT_OPCODE_V(CPL_TX_PKT_XT) | TXPKT_INTF_V(pi->tx_chan) | ctrl0 1588 drivers/net/ethernet/chelsio/cxgb4/sge.c ctrl0 |= TXPKT_TSTAMP_F; ctrl0 1591 drivers/net/ethernet/chelsio/cxgb4/sge.c ctrl0 |= TXPKT_OVLAN_IDX_V(q->dcb_prio); ctrl0 1593 drivers/net/ethernet/chelsio/cxgb4/sge.c ctrl0 |= TXPKT_T5_OVLAN_IDX_V(q->dcb_prio); ctrl0 1595 drivers/net/ethernet/chelsio/cxgb4/sge.c cpl->ctrl0 = htonl(ctrl0); ctrl0 1887 drivers/net/ethernet/chelsio/cxgb4/sge.c cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | ctrl0 819 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h __be32 ctrl0; ctrl0 1357 drivers/net/ethernet/chelsio/cxgb4vf/sge.c cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE_V(CPL_TX_PKT_XT) | ctrl0 423 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c u32 addr, val, ctrl0; ctrl0 436 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c ctrl0 = HINIC_AEQ_CTRL_0_SET(msix_entry->entry, INT_IDX) | ctrl0 442 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl0; ctrl0 457 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c ctrl0 = HINIC_CEQ_CTRL_0_SET(msix_entry->entry, INTR_IDX) | ctrl0 464 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.c val |= ctrl0; ctrl0 228 drivers/net/ethernet/intel/ixgb/ixgb_main.c u32 ctrl0 = IXGB_READ_REG(hw, CTRL0); ctrl0 230 drivers/net/ethernet/intel/ixgb/ixgb_main.c if (!(ctrl0 & IXGB_CTRL0_JFE)) { ctrl0 231 drivers/net/ethernet/intel/ixgb/ixgb_main.c ctrl0 |= IXGB_CTRL0_JFE; ctrl0 232 drivers/net/ethernet/intel/ixgb/ixgb_main.c IXGB_WRITE_REG(hw, CTRL0, ctrl0); ctrl0 292 drivers/net/ethernet/intel/ixgb/ixgb_main.c u32 ctrl0 = IXGB_READ_REG(hw, CTRL0); ctrl0 293 drivers/net/ethernet/intel/ixgb/ixgb_main.c if (!(ctrl0 & IXGB_CTRL0_JFE)) { ctrl0 294 drivers/net/ethernet/intel/ixgb/ixgb_main.c ctrl0 |= IXGB_CTRL0_JFE; ctrl0 295 drivers/net/ethernet/intel/ixgb/ixgb_main.c IXGB_WRITE_REG(hw, CTRL0, ctrl0); ctrl0 4911 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 old_ctrl0, ctrl0; ctrl0 4914 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); ctrl0 4917 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS; ctrl0 4920 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; ctrl0 4922 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; ctrl0 4925 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; ctrl0 4927 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; ctrl0 4933 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (old_ctrl0 != ctrl0) ctrl0 4934 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); ctrl0 4949 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 old_ctrl0, ctrl0; ctrl0 4954 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); ctrl0 4963 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; ctrl0 5027 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; ctrl0 5053 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK || ctrl0 5068 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (old_ctrl0 != ctrl0) ctrl0 5069 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); ctrl0 1113 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8) ctrl0 1117 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8) ctrl0 1120 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8) ctrl0 1263 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) ctrl0 1388 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7) ctrl0 1392 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1) ctrl0 1394 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1) ctrl0 1396 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1) ctrl0 1398 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) ctrl0 1403 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1) ctrl0 1405 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0) vxge_bVALn(ctrl0, 17, 1) ctrl0 1407 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 18, 1) ctrl0 1409 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 19, 1) ctrl0 1411 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) vxge_bVALn(ctrl0, 20, 4) ctrl0 1413 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0) vxge_bVALn(ctrl0, 24, 1) ctrl0 1415 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0) vxge_bVALn(ctrl0, 25, 2) ctrl0 1417 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0) vxge_bVALn(ctrl0, 27, 5) ctrl0 1419 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 32, 16) ctrl0 1421 drivers/net/ethernet/neterion/vxge/vxge-config.h #define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 48, 16) ctrl0 360 drivers/net/wireless/ath/ath6kl/htc_mbox.c int ctrl0, int ctrl1) ctrl0 371 drivers/net/wireless/ath/ath6kl/htc_mbox.c hdr->ctrl[0] = ctrl0; ctrl0 141 drivers/net/wireless/ath/ath9k/ar9003_paprd.c static const u32 ctrl0[3] = { ctrl0 184 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl0[i], ctrl0 198 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, ctrl0[i], ctrl0 200 drivers/phy/samsung/phy-exynos5250-usb2.c u32 ctrl0; ctrl0 244 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); ctrl0 246 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 &= ~EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK; ctrl0 247 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 |= drv->ref_reg_val << ctrl0 251 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST | ctrl0 256 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 |= EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST | ctrl0 259 drivers/phy/samsung/phy-exynos5250-usb2.c writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); ctrl0 261 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 &= ~(EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST | ctrl0 263 drivers/phy/samsung/phy-exynos5250-usb2.c writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); ctrl0 326 drivers/phy/samsung/phy-exynos5250-usb2.c u32 ctrl0; ctrl0 341 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 = readl(drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); ctrl0 342 drivers/phy/samsung/phy-exynos5250-usb2.c ctrl0 |= (EXYNOS_5250_HOSTPHYCTRL0_SIDDQ | ctrl0 347 drivers/phy/samsung/phy-exynos5250-usb2.c writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); ctrl0 724 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0, ctrl1; ctrl0 729 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); ctrl0 735 drivers/pinctrl/intel/pinctrl-cherryview.c if (ctrl0 & CHV_PADCTRL0_GPIOEN) { ctrl0 740 drivers/pinctrl/intel/pinctrl-cherryview.c mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; ctrl0 746 drivers/pinctrl/intel/pinctrl-cherryview.c seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); ctrl0 942 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0; ctrl0 946 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; ctrl0 948 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; ctrl0 950 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; ctrl0 951 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl0, reg); ctrl0 974 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0, ctrl1; ctrl0 979 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); ctrl0 983 drivers/pinctrl/intel/pinctrl-cherryview.c term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; ctrl0 992 drivers/pinctrl/intel/pinctrl-cherryview.c if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) ctrl0 1010 drivers/pinctrl/intel/pinctrl-cherryview.c if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) ctrl0 1032 drivers/pinctrl/intel/pinctrl-cherryview.c cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; ctrl0 1053 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0, pull; ctrl0 1056 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(reg); ctrl0 1060 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); ctrl0 1064 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); ctrl0 1082 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; ctrl0 1086 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); ctrl0 1100 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 |= pull; ctrl0 1108 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl0, reg); ctrl0 1241 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0, cfg; ctrl0 1244 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); ctrl0 1247 drivers/pinctrl/intel/pinctrl-cherryview.c cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; ctrl0 1251 drivers/pinctrl/intel/pinctrl-cherryview.c return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); ctrl0 1252 drivers/pinctrl/intel/pinctrl-cherryview.c return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); ctrl0 1260 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0; ctrl0 1265 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(reg); ctrl0 1268 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; ctrl0 1270 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; ctrl0 1272 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl0, reg); ctrl0 1280 drivers/pinctrl/intel/pinctrl-cherryview.c u32 ctrl0, direction; ctrl0 1284 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); ctrl0 1287 drivers/pinctrl/intel/pinctrl-cherryview.c direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; ctrl0 64 drivers/power/supply/tps65090-charger.c uint8_t ctrl0 = 0; ctrl0 70 drivers/power/supply/tps65090-charger.c &ctrl0); ctrl0 78 drivers/power/supply/tps65090-charger.c (ctrl0 | TPS65090_CHARGER_ENABLE)); ctrl0 175 drivers/spi/spi-mxs.c u32 ctrl0; ctrl0 192 drivers/spi/spi-mxs.c ctrl0 = readl(ssp->base + HW_SSP_CTRL0); ctrl0 193 drivers/spi/spi-mxs.c ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC | ctrl0 195 drivers/spi/spi-mxs.c ctrl0 |= BM_SSP_CTRL0_DATA_XFER; ctrl0 198 drivers/spi/spi-mxs.c ctrl0 |= BM_SSP_CTRL0_READ; ctrl0 210 drivers/spi/spi-mxs.c ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC; ctrl0 213 drivers/spi/spi-mxs.c ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT; ctrl0 214 drivers/spi/spi-mxs.c ctrl0 |= min; ctrl0 217 drivers/spi/spi-mxs.c dma_xfer[sg_count].pio[0] = ctrl0; ctrl0 275 drivers/staging/ralink-gdma/ralink-gdma.c u32 ctrl0, ctrl1; ctrl0 278 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)); ctrl0 279 drivers/staging/ralink-gdma/ralink-gdma.c if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) { ctrl0 281 drivers/staging/ralink-gdma/ralink-gdma.c chan->id, ctrl0); ctrl0 290 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED | ctrl0 296 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED | ctrl0 306 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = GDMA_REG_CTRL0_SW_MODE | ctrl0 315 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | ctrl0 327 drivers/staging/ralink-gdma/ralink-gdma.c gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0); ctrl0 352 drivers/staging/ralink-gdma/ralink-gdma.c u32 ctrl0, ctrl1; ctrl0 355 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)); ctrl0 356 drivers/staging/ralink-gdma/ralink-gdma.c if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) { ctrl0 358 drivers/staging/ralink-gdma/ralink-gdma.c chan->id, ctrl0); ctrl0 367 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED; ctrl0 373 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED; ctrl0 380 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 = GDMA_REG_CTRL0_SW_MODE; ctrl0 390 drivers/staging/ralink-gdma/ralink-gdma.c ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | ctrl0 402 drivers/staging/ralink-gdma/ralink-gdma.c gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0); ctrl0 325 drivers/thermal/armada_thermal.c u32 ctrl0; ctrl0 334 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0); ctrl0 335 drivers/thermal/armada_thermal.c ctrl0 &= ~CONTROL0_TSEN_START; ctrl0 336 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); ctrl0 339 drivers/thermal/armada_thermal.c ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT); ctrl0 344 drivers/thermal/armada_thermal.c ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL << ctrl0 347 drivers/thermal/armada_thermal.c ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT); ctrl0 348 drivers/thermal/armada_thermal.c ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT; ctrl0 352 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); ctrl0 356 drivers/thermal/armada_thermal.c ctrl0 |= CONTROL0_TSEN_START; ctrl0 357 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control0_off, ctrl0); ctrl0 1025 drivers/video/fbdev/mmp/hw/mmp_ctrl.h u32 ctrl0; ctrl0 1057 drivers/video/fbdev/mmp/hw/mmp_ctrl.h u32 ctrl0; ctrl0 555 sound/soc/codecs/adau17x1.c unsigned int ctrl0, ctrl1; ctrl0 560 sound/soc/codecs/adau17x1.c ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER; ctrl0 564 sound/soc/codecs/adau17x1.c ctrl0 = 0; ctrl0 583 sound/soc/codecs/adau17x1.c ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; ctrl0 588 sound/soc/codecs/adau17x1.c ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; ctrl0 599 sound/soc/codecs/adau17x1.c ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; ctrl0 605 sound/soc/codecs/adau17x1.c ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; ctrl0 613 sound/soc/codecs/adau17x1.c ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL; ctrl0 615 sound/soc/codecs/adau17x1.c regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0); ctrl0 300 sound/soc/codecs/adau1977.c unsigned int ctrl0, ctrl0_mask; ctrl0 318 sound/soc/codecs/adau1977.c ctrl0 = fs; ctrl0 323 sound/soc/codecs/adau1977.c ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT; ctrl0 326 sound/soc/codecs/adau1977.c ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT; ctrl0 368 sound/soc/codecs/adau1977.c ctrl0_mask, ctrl0); ctrl0 500 sound/soc/codecs/adau1977.c unsigned int ctrl0, ctrl1, drv; ctrl0 550 sound/soc/codecs/adau1977.c ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2; ctrl0 553 sound/soc/codecs/adau1977.c ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4; ctrl0 556 sound/soc/codecs/adau1977.c ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8; ctrl0 559 sound/soc/codecs/adau1977.c ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16; ctrl0 586 sound/soc/codecs/adau1977.c ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0); ctrl0 620 sound/soc/codecs/adau1977.c unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0; ctrl0 658 sound/soc/codecs/adau1977.c ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S; ctrl0 661 sound/soc/codecs/adau1977.c ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ; ctrl0 665 sound/soc/codecs/adau1977.c ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT; ctrl0 671 sound/soc/codecs/adau1977.c ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S; ctrl0 676 sound/soc/codecs/adau1977.c ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ; ctrl0 694 sound/soc/codecs/adau1977.c ctrl0);