ctr_addr          170 drivers/staging/most/dim2/hal.c static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx)
ctr_addr          172 drivers/staging/most/dim2/hal.c 	dim2_transfer_madr(ctr_addr);
ctr_addr          177 drivers/staging/most/dim2/hal.c static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value)
ctr_addr          197 drivers/staging/most/dim2/hal.c 	dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr);
ctr_addr          200 drivers/staging/most/dim2/hal.c static inline void dim2_write_ctr(u32 ctr_addr, const u32 *value)
ctr_addr          204 drivers/staging/most/dim2/hal.c 	dim2_write_ctr_mask(ctr_addr, mask, value);
ctr_addr          207 drivers/staging/most/dim2/hal.c static inline void dim2_clear_ctr(u32 ctr_addr)
ctr_addr          211 drivers/staging/most/dim2/hal.c 	dim2_write_ctr(ctr_addr, value);
ctr_addr          227 drivers/staging/most/dim2/hal.c 	u8 const ctr_addr = cat_base + ch_addr / 8;
ctr_addr          235 drivers/staging/most/dim2/hal.c 	dim2_write_ctr_mask(ctr_addr, mask, value);
ctr_addr          240 drivers/staging/most/dim2/hal.c 	u8 const ctr_addr = cat_base + ch_addr / 8;
ctr_addr          247 drivers/staging/most/dim2/hal.c 	dim2_write_ctr_mask(ctr_addr, mask, value);
ctr_addr          343 drivers/staging/most/dim2/hal.c 	u32 ctr_addr;
ctr_addr          345 drivers/staging/most/dim2/hal.c 	for (ctr_addr = 0; ctr_addr < 0x90; ctr_addr++)
ctr_addr          346 drivers/staging/most/dim2/hal.c 		dim2_clear_ctr(ctr_addr);