ctr 30 arch/alpha/oprofile/common.c static struct op_counter_config ctr[20]; ctr 39 arch/alpha/oprofile/common.c model->handle_interrupt(which, regs, ctr); ctr 60 arch/alpha/oprofile/common.c if (ctr[i].enabled) ctr 65 arch/alpha/oprofile/common.c model->reg_setup(®, ctr, &sys); ctr 120 arch/alpha/oprofile/common.c oprofilefs_create_ulong(dir, "enabled", &ctr[i].enabled); ctr 121 arch/alpha/oprofile/common.c oprofilefs_create_ulong(dir, "event", &ctr[i].event); ctr 122 arch/alpha/oprofile/common.c oprofilefs_create_ulong(dir, "count", &ctr[i].count); ctr 124 arch/alpha/oprofile/common.c oprofilefs_create_ulong(dir, "kernel", &ctr[i].kernel); ctr 125 arch/alpha/oprofile/common.c oprofilefs_create_ulong(dir, "user", &ctr[i].user); ctr 126 arch/alpha/oprofile/common.c oprofilefs_create_ulong(dir, "unit_mask", &ctr[i].unit_mask); ctr 21 arch/alpha/oprofile/op_model_ev4.c struct op_counter_config *ctr, ctr 39 arch/alpha/oprofile/op_model_ev4.c ctl |= (ctr[0].enabled ? ctr[0].event << 8 : 14 << 8); ctr 40 arch/alpha/oprofile/op_model_ev4.c ctl |= (ctr[1].enabled ? (ctr[1].event - 16) << 32 : 7ul << 32); ctr 48 arch/alpha/oprofile/op_model_ev4.c count = ctr[0].count; ctr 53 arch/alpha/oprofile/op_model_ev4.c ctr[0].count = count; ctr 54 arch/alpha/oprofile/op_model_ev4.c ctl |= (ctr[0].enabled && hilo) << 3; ctr 56 arch/alpha/oprofile/op_model_ev4.c count = ctr[1].count; ctr 61 arch/alpha/oprofile/op_model_ev4.c ctr[1].count = count; ctr 62 arch/alpha/oprofile/op_model_ev4.c ctl |= (ctr[1].enabled && hilo); ctr 94 arch/alpha/oprofile/op_model_ev4.c struct op_counter_config *ctr) ctr 98 arch/alpha/oprofile/op_model_ev4.c if (!ctr[which].enabled) ctr 26 arch/alpha/oprofile/op_model_ev5.c struct op_counter_config *ctr, ctr 47 arch/alpha/oprofile/op_model_ev5.c unsigned long event = ctr[i].event; ctr 48 arch/alpha/oprofile/op_model_ev5.c if (!ctr[i].enabled) ctr 91 arch/alpha/oprofile/op_model_ev5.c unsigned long max, hilo, count = ctr[i].count; ctr 92 arch/alpha/oprofile/op_model_ev5.c if (!ctr[i].enabled) ctr 103 arch/alpha/oprofile/op_model_ev5.c ctr[i].count = count; ctr 117 arch/alpha/oprofile/op_model_ev5.c struct op_counter_config *ctr, ctr 120 arch/alpha/oprofile/op_model_ev5.c common_reg_setup(reg, ctr, sys, 19, 22); ctr 125 arch/alpha/oprofile/op_model_ev5.c struct op_counter_config *ctr, ctr 128 arch/alpha/oprofile/op_model_ev5.c common_reg_setup(reg, ctr, sys, 8, 11); ctr 157 arch/alpha/oprofile/op_model_ev5.c ev5_reset_ctr(struct op_register_config *reg, unsigned long ctr) ctr 161 arch/alpha/oprofile/op_model_ev5.c mask = (ctr == 0 ? 0xfffful << 48 ctr 162 arch/alpha/oprofile/op_model_ev5.c : ctr == 1 ? 0xfffful << 32 ctr 184 arch/alpha/oprofile/op_model_ev5.c struct op_counter_config *ctr) ctr 21 arch/alpha/oprofile/op_model_ev6.c struct op_counter_config *ctr, ctr 29 arch/alpha/oprofile/op_model_ev6.c if (ctr[0].enabled && ctr[0].event) ctr 30 arch/alpha/oprofile/op_model_ev6.c ctl |= (ctr[0].event & 1) << 4; ctr 31 arch/alpha/oprofile/op_model_ev6.c if (ctr[1].enabled) ctr 32 arch/alpha/oprofile/op_model_ev6.c ctl |= (ctr[1].event - 2) & 15; ctr 47 arch/alpha/oprofile/op_model_ev6.c unsigned long count = ctr[i].count; ctr 48 arch/alpha/oprofile/op_model_ev6.c if (!ctr[i].enabled) ctr 53 arch/alpha/oprofile/op_model_ev6.c ctr[i].count = count; ctr 79 arch/alpha/oprofile/op_model_ev6.c ev6_reset_ctr(struct op_register_config *reg, unsigned long ctr) ctr 81 arch/alpha/oprofile/op_model_ev6.c wrperfmon(6, reg->reset_values | (1 << ctr)); ctr 86 arch/alpha/oprofile/op_model_ev6.c struct op_counter_config *ctr) ctr 22 arch/alpha/oprofile/op_model_ev67.c struct op_counter_config *ctr, ctr 32 arch/alpha/oprofile/op_model_ev67.c if (ctr[1].enabled) { ctr 33 arch/alpha/oprofile/op_model_ev67.c ctl |= (ctr[1].event & 3) << 2; ctr 35 arch/alpha/oprofile/op_model_ev67.c if (ctr[0].event == 0) /* cycles */ ctr 52 arch/alpha/oprofile/op_model_ev67.c unsigned long count = ctr[i].count; ctr 53 arch/alpha/oprofile/op_model_ev67.c if (!ctr[i].enabled) ctr 58 arch/alpha/oprofile/op_model_ev67.c ctr[i].count = count; ctr 84 arch/alpha/oprofile/op_model_ev67.c ev67_reset_ctr(struct op_register_config *reg, unsigned long ctr) ctr 86 arch/alpha/oprofile/op_model_ev67.c wrperfmon(6, reg->reset_values | (1 << ctr)); ctr 133 arch/alpha/oprofile/op_model_ev67.c struct op_counter_config *ctr, unsigned long event) ctr 138 arch/alpha/oprofile/op_model_ev67.c if (ctr[fake_counter].enabled) ctr 144 arch/alpha/oprofile/op_model_ev67.c struct op_counter_config *ctr) ctr 200 arch/alpha/oprofile/op_model_ev67.c ctr, PM_ITB_MISS); ctr 206 arch/alpha/oprofile/op_model_ev67.c op_add_pm(pmpc, kern, which, ctr, ctr 213 arch/alpha/oprofile/op_model_ev67.c op_add_pm(pmpc, kern, which, ctr, PM_DTB_MISS); ctr 216 arch/alpha/oprofile/op_model_ev67.c op_add_pm(pmpc, kern, which, ctr, PM_UNALIGNED); ctr 236 arch/alpha/oprofile/op_model_ev67.c op_add_pm(pmpc, kern, which, ctr, PM_MISPREDICT); ctr 244 arch/alpha/oprofile/op_model_ev67.c op_add_pm(pmpc, kern, which, ctr, PM_STALLED); ctr 250 arch/alpha/oprofile/op_model_ev67.c op_add_pm(pmpc, kern, which, ctr, PM_TAKEN); ctr 38 arch/arc/include/asm/atomic.h : [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \ ctr 60 arch/arc/include/asm/atomic.h : [ctr] "r" (&v->counter), \ ctr 87 arch/arc/include/asm/atomic.h : [ctr] "r" (&v->counter), \ ctr 44 arch/arm/crypto/aes-ce-glue.c int rounds, int blocks, u8 ctr[]); ctr 38 arch/arm/crypto/aes-neonbs-glue.c int rounds, int blocks, u8 ctr[], u8 final[]); ctr 251 arch/arm/mm/init.c u32 size, ctr; ctr 253 arch/arm/mm/init.c asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); ctr 255 arch/arm/mm/init.c size = 1 << ((ctr & 0xf) + 2); ctr 14 arch/arm/plat-versatile/sched-clock.c static void __iomem *ctr; ctr 18 arch/arm/plat-versatile/sched-clock.c if (ctr) ctr 19 arch/arm/plat-versatile/sched-clock.c return readl(ctr); ctr 26 arch/arm/plat-versatile/sched-clock.c ctr = reg; ctr 37 arch/arm64/crypto/aes-ce-ccm-glue.c u8 ctr[]); ctr 41 arch/arm64/crypto/aes-ce-ccm-glue.c u8 ctr[]); ctr 43 arch/arm64/crypto/aes-ce-ccm-glue.c asmlinkage void ce_aes_ccm_final(u8 mac[], u8 const ctr[], u32 const rk[], ctr 90 arch/arm64/crypto/aes-glue.c int rounds, int blocks, u8 ctr[]); ctr 63 arch/arm64/crypto/ghash-ce-glue.c u8 ctr[], u32 const rk[], int rounds, ctr 68 arch/arm64/crypto/ghash-ce-glue.c u8 ctr[], u32 const rk[], int rounds); ctr 24 arch/arm64/include/asm/cache.h #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) ctr 111 arch/arm64/include/asm/cache.h u32 ctr = read_cpuid_cachetype(); ctr 113 arch/arm64/include/asm/cache.h if (!(ctr & BIT(CTR_IDC_SHIFT))) { ctr 118 arch/arm64/include/asm/cache.h ctr |= BIT(CTR_IDC_SHIFT); ctr 121 arch/arm64/include/asm/cache.h return ctr; ctr 917 arch/arm64/kernel/cpufeature.c u64 ctr; ctr 920 arch/arm64/kernel/cpufeature.c ctr = arm64_ftr_reg_ctrel0.sys_val; ctr 922 arch/arm64/kernel/cpufeature.c ctr = read_cpuid_effective_cachetype(); ctr 924 arch/arm64/kernel/cpufeature.c return ctr & BIT(CTR_IDC_SHIFT); ctr 942 arch/arm64/kernel/cpufeature.c u64 ctr; ctr 945 arch/arm64/kernel/cpufeature.c ctr = arm64_ftr_reg_ctrel0.sys_val; ctr 947 arch/arm64/kernel/cpufeature.c ctr = read_cpuid_cachetype(); ctr 949 arch/arm64/kernel/cpufeature.c return ctr & BIT(CTR_DIC_SHIFT); ctr 1357 arch/mips/kernel/perf_event_mipsxx.c int ctr = mipspmu.num_counters; ctr 1362 arch/mips/kernel/perf_event_mipsxx.c ctr--; ctr 1363 arch/mips/kernel/perf_event_mipsxx.c cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); ctr 1364 arch/mips/kernel/perf_event_mipsxx.c mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & ctr 1366 arch/mips/kernel/perf_event_mipsxx.c } while (ctr > 0); ctr 1373 arch/mips/kernel/perf_event_mipsxx.c int ctr = mipspmu.num_counters; ctr 1376 arch/mips/kernel/perf_event_mipsxx.c ctr--; ctr 1377 arch/mips/kernel/perf_event_mipsxx.c mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); ctr 1378 arch/mips/kernel/perf_event_mipsxx.c } while (ctr > 0); ctr 25 arch/mips/oprofile/common.c static struct op_counter_config ctr[20]; ctr 30 arch/mips/oprofile/common.c model->reg_setup(ctr); ctr 49 arch/mips/oprofile/common.c oprofilefs_create_ulong(dir, "enabled", &ctr[i].enabled); ctr 50 arch/mips/oprofile/common.c oprofilefs_create_ulong(dir, "event", &ctr[i].event); ctr 51 arch/mips/oprofile/common.c oprofilefs_create_ulong(dir, "count", &ctr[i].count); ctr 52 arch/mips/oprofile/common.c oprofilefs_create_ulong(dir, "kernel", &ctr[i].kernel); ctr 53 arch/mips/oprofile/common.c oprofilefs_create_ulong(dir, "user", &ctr[i].user); ctr 54 arch/mips/oprofile/common.c oprofilefs_create_ulong(dir, "exl", &ctr[i].exl); ctr 56 arch/mips/oprofile/common.c oprofilefs_create_ulong(dir, "unit_mask", &ctr[i].unit_mask); ctr 62 arch/mips/oprofile/op_model_loongson3.c static void loongson3_reg_setup(struct op_counter_config *ctr) ctr 71 arch/mips/oprofile/op_model_loongson3.c if (ctr[0].enabled) { ctr 72 arch/mips/oprofile/op_model_loongson3.c control1 |= LOONGSON3_PERFCTRL_EVENT(0, ctr[0].event) | ctr 74 arch/mips/oprofile/op_model_loongson3.c if (ctr[0].kernel) ctr 76 arch/mips/oprofile/op_model_loongson3.c if (ctr[0].user) ctr 78 arch/mips/oprofile/op_model_loongson3.c reg.reset_counter1 = 0x8000000000000000ULL - ctr[0].count; ctr 81 arch/mips/oprofile/op_model_loongson3.c if (ctr[1].enabled) { ctr 82 arch/mips/oprofile/op_model_loongson3.c control2 |= LOONGSON3_PERFCTRL_EVENT(1, ctr[1].event) | ctr 84 arch/mips/oprofile/op_model_loongson3.c if (ctr[1].kernel) ctr 86 arch/mips/oprofile/op_model_loongson3.c if (ctr[1].user) ctr 88 arch/mips/oprofile/op_model_loongson3.c reg.reset_counter2 = 0x8000000000000000ULL - ctr[1].count; ctr 91 arch/mips/oprofile/op_model_loongson3.c if (ctr[0].enabled) ctr 93 arch/mips/oprofile/op_model_loongson3.c if (ctr[1].enabled) ctr 98 arch/mips/oprofile/op_model_loongson3.c reg.ctr1_enable = ctr[0].enabled; ctr 99 arch/mips/oprofile/op_model_loongson3.c reg.ctr2_enable = ctr[1].enabled; ctr 135 arch/mips/oprofile/op_model_mipsxx.c static void mipsxx_reg_setup(struct op_counter_config *ctr) ctr 145 arch/mips/oprofile/op_model_mipsxx.c if (!ctr[i].enabled) ctr 148 arch/mips/oprofile/op_model_mipsxx.c reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | ctr 150 arch/mips/oprofile/op_model_mipsxx.c if (ctr[i].kernel) ctr 152 arch/mips/oprofile/op_model_mipsxx.c if (ctr[i].user) ctr 154 arch/mips/oprofile/op_model_mipsxx.c if (ctr[i].exl) ctr 158 arch/mips/oprofile/op_model_mipsxx.c reg.counter[i] = 0x80000000 - ctr[i].count; ctr 22 arch/powerpc/include/asm/cell-pmu.h #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1)))) ctr 52 arch/powerpc/include/asm/cell-pmu.h #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7))) ctr 68 arch/powerpc/include/asm/cell-pmu.h extern u32 cbe_read_ctr(u32 cpu, u32 ctr); ctr 69 arch/powerpc/include/asm/cell-pmu.h extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val); ctr 71 arch/powerpc/include/asm/cell-pmu.h extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr); ctr 72 arch/powerpc/include/asm/cell-pmu.h extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val); ctr 360 arch/powerpc/include/asm/kvm_book3s.h vcpu->arch.regs.ctr = val; ctr 365 arch/powerpc/include/asm/kvm_book3s.h return vcpu->arch.regs.ctr; ctr 593 arch/powerpc/include/asm/kvm_book3s_64.h vcpu->arch.regs.ctr = vcpu->arch.ctr_tm; ctr 610 arch/powerpc/include/asm/kvm_book3s_64.h vcpu->arch.ctr_tm = vcpu->arch.regs.ctr; ctr 142 arch/powerpc/include/asm/kvm_book3s_asm.h ulong ctr; ctr 64 arch/powerpc/include/asm/kvm_booke.h vcpu->arch.regs.ctr = val; ctr 69 arch/powerpc/include/asm/kvm_booke.h return vcpu->arch.regs.ctr; ctr 496 arch/powerpc/include/asm/ps3.h u32 ps3_read_ctr(u32 cpu, u32 ctr); ctr 497 arch/powerpc/include/asm/ps3.h void ps3_write_ctr(u32 cpu, u32 ctr, u32 val); ctr 499 arch/powerpc/include/asm/ps3.h u32 ps3_read_pm07_control(u32 cpu, u32 ctr); ctr 500 arch/powerpc/include/asm/ps3.h void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val); ctr 35 arch/powerpc/include/asm/ptrace.h unsigned long ctr; ctr 39 arch/powerpc/include/uapi/asm/kvm.h __u64 ctr; ctr 42 arch/powerpc/include/uapi/asm/ptrace.h unsigned long ctr; ctr 312 arch/powerpc/kernel/asm-offsets.c STACK_PT_REGS_OFFSET(_CTR, ctr); ctr 444 arch/powerpc/kernel/asm-offsets.c OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); ctr 618 arch/powerpc/kernel/asm-offsets.c SVCPU_FIELD(SVCPU_CTR, ctr); ctr 711 arch/powerpc/kernel/asm-offsets.c OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); ctr 229 arch/powerpc/kernel/kgdb.c PACK64(ptr, regs->ctr); ctr 317 arch/powerpc/kernel/kgdb.c { "ctr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ctr) }, ctr 20 arch/powerpc/kernel/ppc32.h unsigned int ctr; ctr 1395 arch/powerpc/kernel/process.c regs->nip, regs->link, regs->ctr); ctr 1721 arch/powerpc/kernel/process.c regs->ctr = 0; ctr 112 arch/powerpc/kernel/ptrace.c REG_OFFSET_NAME(ctr), ctr 3376 arch/powerpc/kernel/ptrace.c BUILD_BUG_ON(offsetof(struct pt_regs, ctr) != ctr 3377 arch/powerpc/kernel/ptrace.c offsetof(struct user_pt_regs, ctr)); ctr 349 arch/powerpc/kernel/signal_64.c err |= __get_user(regs->ctr, &sc->gp_regs[PT_CTR]); ctr 463 arch/powerpc/kernel/signal_64.c err |= __get_user(regs->ctr, &tm_sc->gp_regs[PT_CTR]); ctr 467 arch/powerpc/kernel/signal_64.c err |= __get_user(tsk->thread.ckpt_regs.ctr, ctr 543 arch/powerpc/kvm/book3s.c regs->ctr = kvmppc_get_ctr(vcpu); ctr 571 arch/powerpc/kvm/book3s.c kvmppc_set_ctr(vcpu, regs->ctr); ctr 99 arch/powerpc/kvm/book3s_emulate.c vcpu->arch.ctr_tm = vcpu->arch.regs.ctr; ctr 118 arch/powerpc/kvm/book3s_emulate.c vcpu->arch.regs.ctr = vcpu->arch.ctr_tm; ctr 426 arch/powerpc/kvm/book3s_hv.c vcpu->arch.regs.ctr, vcpu->arch.regs.link); ctr 169 arch/powerpc/kvm/book3s_pr.c svcpu->ctr = vcpu->arch.regs.ctr; ctr 251 arch/powerpc/kvm/book3s_pr.c vcpu->arch.regs.ctr = svcpu->ctr; ctr 72 arch/powerpc/kvm/booke.c vcpu->arch.regs.ctr); ctr 1437 arch/powerpc/kvm/booke.c regs->ctr = vcpu->arch.regs.ctr; ctr 1468 arch/powerpc/kvm/booke.c vcpu->arch.regs.ctr = regs->ctr; ctr 92 arch/powerpc/lib/sstep.c if (((bo >> 1) & 1) ^ (regs->ctr == 1)) ctr 1223 arch/powerpc/lib/sstep.c imm = (instr & 0x400)? regs->ctr: regs->link; ctr 2776 arch/powerpc/lib/sstep.c --regs->ctr; ctr 2808 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = regs->ctr; ctr 2824 arch/powerpc/lib/sstep.c regs->ctr = op->val; ctr 65 arch/powerpc/mm/nohash/8xx.c unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000; ctr 72 arch/powerpc/mm/nohash/8xx.c mtspr(SPRN_MD_CTR, ctr | (i << 8)); ctr 24 arch/powerpc/oprofile/common.c static struct op_counter_config ctr[OP_MAX_COUNTER]; ctr 31 arch/powerpc/oprofile/common.c model->handle_interrupt(regs, ctr); ctr 38 arch/powerpc/oprofile/common.c ret = model->cpu_setup(ctr); ctr 56 arch/powerpc/oprofile/common.c op_per_cpu_rc = model->reg_setup(ctr, &sys, model->num_counters); ctr 86 arch/powerpc/oprofile/common.c ret = model->start(ctr); ctr 96 arch/powerpc/oprofile/common.c return model->global_start(ctr); ctr 161 arch/powerpc/oprofile/common.c oprofilefs_create_ulong(dir, "enabled", &ctr[i].enabled); ctr 162 arch/powerpc/oprofile/common.c oprofilefs_create_ulong(dir, "event", &ctr[i].event); ctr 163 arch/powerpc/oprofile/common.c oprofilefs_create_ulong(dir, "count", &ctr[i].count); ctr 172 arch/powerpc/oprofile/common.c oprofilefs_create_ulong(dir, "kernel", &ctr[i].kernel); ctr 173 arch/powerpc/oprofile/common.c oprofilefs_create_ulong(dir, "user", &ctr[i].user); ctr 175 arch/powerpc/oprofile/common.c oprofilefs_create_ulong(dir, "unit_mask", &ctr[i].unit_mask); ctr 78 arch/powerpc/oprofile/op_model_7450.c static int fsl7450_cpu_setup(struct op_counter_config *ctr) ctr 92 arch/powerpc/oprofile/op_model_7450.c static int fsl7450_reg_setup(struct op_counter_config *ctr, ctr 105 arch/powerpc/oprofile/op_model_7450.c reset_value[i] = 0x80000000UL - ctr[i].count; ctr 108 arch/powerpc/oprofile/op_model_7450.c mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event) ctr 109 arch/powerpc/oprofile/op_model_7450.c | mmcr0_event2(ctr[1].event); ctr 119 arch/powerpc/oprofile/op_model_7450.c mmcr1_val = mmcr1_event3(ctr[2].event) ctr 120 arch/powerpc/oprofile/op_model_7450.c | mmcr1_event4(ctr[3].event); ctr 122 arch/powerpc/oprofile/op_model_7450.c mmcr1_val |= mmcr1_event5(ctr[4].event) ctr 123 arch/powerpc/oprofile/op_model_7450.c | mmcr1_event6(ctr[5].event); ctr 131 arch/powerpc/oprofile/op_model_7450.c static int fsl7450_start(struct op_counter_config *ctr) ctr 138 arch/powerpc/oprofile/op_model_7450.c if (ctr[i].enabled) ctr 169 arch/powerpc/oprofile/op_model_7450.c struct op_counter_config *ctr) ctr 185 arch/powerpc/oprofile/op_model_7450.c if (oprofile_running && ctr[i].enabled) { ctr 282 arch/powerpc/oprofile/op_model_cell.c static void set_pm_event(u32 ctr, int event, u32 unit_mask) ctr 291 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES; ctr 292 arch/powerpc/oprofile/op_model_cell.c p = &(pm_signal[ctr]); ctr 299 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] = 0; ctr 309 arch/powerpc/oprofile/op_model_cell.c p = &(pm_signal[ctr]); ctr 315 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] = 0; ctr 316 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles); ctr 317 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity); ctr 318 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control); ctr 343 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit); ctr 345 arch/powerpc/oprofile/op_model_cell.c pm_regs.pm07_cntrl[ctr] = 0; ctr 424 arch/powerpc/oprofile/op_model_cell.c static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl) ctr 427 arch/powerpc/oprofile/op_model_cell.c pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE; ctr 428 arch/powerpc/oprofile/op_model_cell.c cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]); ctr 559 arch/powerpc/oprofile/op_model_cell.c static int cell_reg_setup_spu_cycles(struct op_counter_config *ctr, ctr 562 arch/powerpc/oprofile/op_model_cell.c spu_cycle_reset = ctr[0].count; ctr 681 arch/powerpc/oprofile/op_model_cell.c static int cell_reg_setup_spu_events(struct op_counter_config *ctr, ctr 736 arch/powerpc/oprofile/op_model_cell.c set_pm_event(0, ctr[0].event, ctr[0].unit_mask); ctr 738 arch/powerpc/oprofile/op_model_cell.c reset_value[0] = 0xFFFFFFFF - ctr[0].count; ctr 750 arch/powerpc/oprofile/op_model_cell.c static int cell_reg_setup_ppu(struct op_counter_config *ctr, ctr 771 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[0][i].evnts = ctr[i].event; ctr 772 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[0][i].masks = ctr[i].unit_mask; ctr 773 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[0][i].enabled = ctr[i].enabled; ctr 785 arch/powerpc/oprofile/op_model_cell.c if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111)) ctr 786 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[1][i].evnts = ctr[i].event + 19; ctr 787 arch/powerpc/oprofile/op_model_cell.c else if (ctr[i].event == 2203) ctr 788 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[1][i].evnts = ctr[i].event; ctr 789 arch/powerpc/oprofile/op_model_cell.c else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215)) ctr 790 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[1][i].evnts = ctr[i].event + 16; ctr 792 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[1][i].evnts = ctr[i].event; ctr 794 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[1][i].masks = ctr[i].unit_mask; ctr 795 arch/powerpc/oprofile/op_model_cell.c pmc_cntrl[1][i].enabled = ctr[i].enabled; ctr 813 arch/powerpc/oprofile/op_model_cell.c reset_value[i] = 0xFFFFFFFF - ctr[i].count; ctr 834 arch/powerpc/oprofile/op_model_cell.c static int cell_reg_setup(struct op_counter_config *ctr, ctr 866 arch/powerpc/oprofile/op_model_cell.c if (ctr[0].event == SPU_CYCLES_EVENT_NUM) { ctr 868 arch/powerpc/oprofile/op_model_cell.c ret = cell_reg_setup_spu_cycles(ctr, sys, num_ctrs); ctr 869 arch/powerpc/oprofile/op_model_cell.c } else if ((ctr[0].event >= SPU_EVENT_NUM_START) && ctr 870 arch/powerpc/oprofile/op_model_cell.c (ctr[0].event <= SPU_EVENT_NUM_STOP)) { ctr 872 arch/powerpc/oprofile/op_model_cell.c spu_cycle_reset = ctr[0].count; ctr 880 arch/powerpc/oprofile/op_model_cell.c cell_reg_setup_spu_events(ctr, sys, num_ctrs); ctr 883 arch/powerpc/oprofile/op_model_cell.c ret = cell_reg_setup_ppu(ctr, sys, num_ctrs); ctr 1241 arch/powerpc/oprofile/op_model_cell.c static int cell_global_start_spu_cycles(struct op_counter_config *ctr) ctr 1331 arch/powerpc/oprofile/op_model_cell.c static int cell_global_start_spu_events(struct op_counter_config *ctr) ctr 1394 arch/powerpc/oprofile/op_model_cell.c static int cell_global_start_ppu(struct op_counter_config *ctr) ctr 1440 arch/powerpc/oprofile/op_model_cell.c static int cell_global_start(struct op_counter_config *ctr) ctr 1443 arch/powerpc/oprofile/op_model_cell.c return cell_global_start_spu_cycles(ctr); ctr 1445 arch/powerpc/oprofile/op_model_cell.c return cell_global_start_spu_events(ctr); ctr 1447 arch/powerpc/oprofile/op_model_cell.c return cell_global_start_ppu(ctr); ctr 1479 arch/powerpc/oprofile/op_model_cell.c struct op_counter_config *ctr) ctr 1513 arch/powerpc/oprofile/op_model_cell.c && ctr[0].enabled) ctr 1597 arch/powerpc/oprofile/op_model_cell.c struct op_counter_config *ctr) ctr 1638 arch/powerpc/oprofile/op_model_cell.c && ctr[i].enabled) { ctr 1670 arch/powerpc/oprofile/op_model_cell.c struct op_counter_config *ctr) ctr 1673 arch/powerpc/oprofile/op_model_cell.c cell_handle_interrupt_ppu(regs, ctr); ctr 1675 arch/powerpc/oprofile/op_model_cell.c cell_handle_interrupt_spu(regs, ctr); ctr 27 arch/powerpc/oprofile/op_model_fsl_emb.c static inline u32 get_pmlca(int ctr) ctr 31 arch/powerpc/oprofile/op_model_fsl_emb.c switch (ctr) { ctr 57 arch/powerpc/oprofile/op_model_fsl_emb.c static inline void set_pmlca(int ctr, u32 pmlca) ctr 59 arch/powerpc/oprofile/op_model_fsl_emb.c switch (ctr) { ctr 130 arch/powerpc/oprofile/op_model_fsl_emb.c static void init_pmc_stop(int ctr) ctr 136 arch/powerpc/oprofile/op_model_fsl_emb.c switch (ctr) { ctr 166 arch/powerpc/oprofile/op_model_fsl_emb.c static void set_pmc_event(int ctr, int event) ctr 170 arch/powerpc/oprofile/op_model_fsl_emb.c pmlca = get_pmlca(ctr); ctr 176 arch/powerpc/oprofile/op_model_fsl_emb.c set_pmlca(ctr, pmlca); ctr 179 arch/powerpc/oprofile/op_model_fsl_emb.c static void set_pmc_user_kernel(int ctr, int user, int kernel) ctr 183 arch/powerpc/oprofile/op_model_fsl_emb.c pmlca = get_pmlca(ctr); ctr 195 arch/powerpc/oprofile/op_model_fsl_emb.c set_pmlca(ctr, pmlca); ctr 198 arch/powerpc/oprofile/op_model_fsl_emb.c static void set_pmc_marked(int ctr, int mark0, int mark1) ctr 200 arch/powerpc/oprofile/op_model_fsl_emb.c u32 pmlca = get_pmlca(ctr); ctr 212 arch/powerpc/oprofile/op_model_fsl_emb.c set_pmlca(ctr, pmlca); ctr 215 arch/powerpc/oprofile/op_model_fsl_emb.c static void pmc_start_ctr(int ctr, int enable) ctr 217 arch/powerpc/oprofile/op_model_fsl_emb.c u32 pmlca = get_pmlca(ctr); ctr 226 arch/powerpc/oprofile/op_model_fsl_emb.c set_pmlca(ctr, pmlca); ctr 255 arch/powerpc/oprofile/op_model_fsl_emb.c static int fsl_emb_cpu_setup(struct op_counter_config *ctr) ctr 265 arch/powerpc/oprofile/op_model_fsl_emb.c set_pmc_event(i, ctr[i].event); ctr 267 arch/powerpc/oprofile/op_model_fsl_emb.c set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel); ctr 273 arch/powerpc/oprofile/op_model_fsl_emb.c static int fsl_emb_reg_setup(struct op_counter_config *ctr, ctr 287 arch/powerpc/oprofile/op_model_fsl_emb.c reset_value[i] = 0x80000000UL - ctr[i].count; ctr 292 arch/powerpc/oprofile/op_model_fsl_emb.c static int fsl_emb_start(struct op_counter_config *ctr) ctr 299 arch/powerpc/oprofile/op_model_fsl_emb.c if (ctr[i].enabled) { ctr 341 arch/powerpc/oprofile/op_model_fsl_emb.c struct op_counter_config *ctr) ctr 354 arch/powerpc/oprofile/op_model_fsl_emb.c if (oprofile_running && ctr[i].enabled) { ctr 79 arch/powerpc/oprofile/op_model_pa6t.c static int pa6t_reg_setup(struct op_counter_config *ctr, ctr 93 arch/powerpc/oprofile/op_model_pa6t.c if (!ctr[pmc].enabled) { ctr 121 arch/powerpc/oprofile/op_model_pa6t.c reset_value[pmc] = (0x1UL << 39) - ctr[pmc].count; ctr 130 arch/powerpc/oprofile/op_model_pa6t.c static int pa6t_cpu_setup(struct op_counter_config *ctr) ctr 150 arch/powerpc/oprofile/op_model_pa6t.c static int pa6t_start(struct op_counter_config *ctr) ctr 158 arch/powerpc/oprofile/op_model_pa6t.c if (ctr[i].enabled) ctr 188 arch/powerpc/oprofile/op_model_pa6t.c struct op_counter_config *ctr) ctr 206 arch/powerpc/oprofile/op_model_pa6t.c if (oprofile_running && ctr[i].enabled) { ctr 92 arch/powerpc/oprofile/op_model_power4.c static int power4_reg_setup(struct op_counter_config *ctr, ctr 125 arch/powerpc/oprofile/op_model_power4.c reset_value[i] = 0x80000000UL - ctr[i].count; ctr 169 arch/powerpc/oprofile/op_model_power4.c static int power4_cpu_setup(struct op_counter_config *ctr) ctr 200 arch/powerpc/oprofile/op_model_power4.c static int power4_start(struct op_counter_config *ctr) ctr 209 arch/powerpc/oprofile/op_model_power4.c if (ctr[i].enabled) { ctr 360 arch/powerpc/oprofile/op_model_power4.c struct op_counter_config *ctr) ctr 385 arch/powerpc/oprofile/op_model_power4.c if (oprofile_running && ctr[i].enabled) { ctr 37 arch/powerpc/perf/8xx-pmu.c int ctr; ctr 41 arch/powerpc/perf/8xx-pmu.c ctr = atomic_read(&instruction_counter); ctr 43 arch/powerpc/perf/8xx-pmu.c } while (ctr != atomic_read(&instruction_counter)); ctr 45 arch/powerpc/perf/8xx-pmu.c return ((s64)ctr << 16) | (counta >> 16); ctr 56 arch/powerpc/perf/perf_regs.c PT_REGS_OFFSET(PERF_REG_POWERPC_CTR, ctr), ctr 113 arch/powerpc/platforms/cell/pmu.c u32 cbe_read_ctr(u32 cpu, u32 ctr) ctr 116 arch/powerpc/platforms/cell/pmu.c u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1); ctr 121 arch/powerpc/platforms/cell/pmu.c val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff); ctr 127 arch/powerpc/platforms/cell/pmu.c void cbe_write_ctr(u32 cpu, u32 ctr, u32 val) ctr 132 arch/powerpc/platforms/cell/pmu.c phys_ctr = ctr & (NR_PHYS_CTRS - 1); ctr 137 arch/powerpc/platforms/cell/pmu.c if (ctr < NR_PHYS_CTRS) ctr 152 arch/powerpc/platforms/cell/pmu.c u32 cbe_read_pm07_control(u32 cpu, u32 ctr) ctr 156 arch/powerpc/platforms/cell/pmu.c if (ctr < NR_CTRS) ctr 157 arch/powerpc/platforms/cell/pmu.c READ_SHADOW_REG(pm07_control, pm07_control[ctr]); ctr 163 arch/powerpc/platforms/cell/pmu.c void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val) ctr 165 arch/powerpc/platforms/cell/pmu.c if (ctr < NR_CTRS) ctr 166 arch/powerpc/platforms/cell/pmu.c WRITE_WO_MMIO(pm07_control[ctr], val); ctr 98 arch/powerpc/platforms/powernv/opal-fadump.h regs->ctr = reg_val; ctr 262 arch/powerpc/platforms/pseries/rtas-fadump.c regs->ctr = (unsigned long)reg_val; ctr 1777 arch/powerpc/xmon/xmon.c fp->ctr, fp->xer, fp->trap); ctr 399 arch/s390/include/asm/cpacf.h [dst] "+a" (r4), [ctr] "+a" (r6) ctr 191 arch/s390/include/asm/cpu_mf.h static inline int __ecctr(u64 ctr, u64 *content) ctr 200 arch/s390/include/asm/cpu_mf.h : "=d" (_content), "=d" (cc) : "d" (ctr) : "cc"); ctr 206 arch/s390/include/asm/cpu_mf.h static inline int ecctr(u64 ctr, u64 *val) ctr 211 arch/s390/include/asm/cpu_mf.h cc = __ecctr(ctr, &content); ctr 67 arch/s390/kernel/perf_cpum_cf_diag.c unsigned int ctr:16; /* 32-47 Number of stored counters */ ctr 386 arch/s390/kernel/perf_cpum_cf_diag.c ctrdata->ctr = ctrset_size; ctr 462 arch/s390/kernel/perf_cpum_cf_diag.c (u64 *)(ctrstop + 1), ctrstart->ctr); ctr 463 arch/s390/kernel/perf_cpum_cf_diag.c offset += ctrstart->ctr * sizeof(u64) + ctr 468 arch/s390/kernel/perf_cpum_cf_diag.c __func__, ctrstart->set, ctrstart->ctr, ctr 22 arch/sparc/kernel/windows.c register int ctr asm("g5"); ctr 24 arch/sparc/kernel/windows.c ctr = 0; ctr 36 arch/sparc/kernel/windows.c : "=&r" (ctr) ctr 37 arch/sparc/kernel/windows.c : "0" (ctr), ctr 57 arch/x86/boot/a20.c int saved, ctr; ctr 62 arch/x86/boot/a20.c saved = ctr = rdfs32(A20_TEST_ADDR); ctr 65 arch/x86/boot/a20.c wrfs32(++ctr, A20_TEST_ADDR); ctr 67 arch/x86/boot/a20.c ok = rdgs32(A20_TEST_ADDR+0x10) ^ ctr; ctr 62 arch/x86/crypto/camellia_aesni_avx2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_ctr_32way) } ctr 65 arch/x86/crypto/camellia_aesni_avx2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_ctr_16way) } ctr 68 arch/x86/crypto/camellia_aesni_avx2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr_2way) } ctr 71 arch/x86/crypto/camellia_aesni_avx2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr) } ctr 81 arch/x86/crypto/camellia_aesni_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_ctr_16way) } ctr 84 arch/x86/crypto/camellia_aesni_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr_2way) } ctr 87 arch/x86/crypto/camellia_aesni_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr) } ctr 1331 arch/x86/crypto/camellia_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr_2way) } ctr 1334 arch/x86/crypto/camellia_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr) } ctr 86 arch/x86/crypto/cast6_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(cast6_ctr_8way) } ctr 89 arch/x86/crypto/cast6_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(cast6_crypt_ctr) } ctr 191 arch/x86/crypto/glue_helper.c gctx->funcs[i].fn_u.ctr(ctx, dst, src, &ctrblk); ctr 213 arch/x86/crypto/glue_helper.c gctx->funcs[gctx->num_funcs - 1].fn_u.ctr(ctx, &tmp, &tmp, ctr 63 arch/x86/crypto/serpent_avx2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_ctr_16way) } ctr 66 arch/x86/crypto/serpent_avx2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_ctr_8way_avx) } ctr 69 arch/x86/crypto/serpent_avx2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(__serpent_crypt_ctr) } ctr 118 arch/x86/crypto/serpent_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_ctr_8way_avx) } ctr 121 arch/x86/crypto/serpent_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(__serpent_crypt_ctr) } ctr 95 arch/x86/crypto/serpent_sse2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_crypt_ctr_xway) } ctr 98 arch/x86/crypto/serpent_sse2_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_crypt_ctr) } ctr 112 arch/x86/crypto/twofish_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_ctr_8way) } ctr 115 arch/x86/crypto/twofish_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr_3way) } ctr 118 arch/x86/crypto/twofish_avx_glue.c .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr) } ctr 355 arch/x86/events/intel/uncore_nhmex.c int ctr, ev_sel; ctr 357 arch/x86/events/intel/uncore_nhmex.c ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >> ctr 363 arch/x86/events/intel/uncore_nhmex.c if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) || ctr 364 arch/x86/events/intel/uncore_nhmex.c (ctr == 2 && ev_sel != 0x4) || ctr == 3) ctr 31 arch/x86/include/asm/crypto/glue_helper.h common_glue_ctr_func_t ctr; ctr 504 arch/x86/oprofile/op_model_p4.c static void pmc_setup_one_p4_counter(unsigned int ctr) ctr 518 arch/x86/oprofile/op_model_p4.c counter_bit = 1 << VIRT_CTR(stag, ctr); ctr 521 arch/x86/oprofile/op_model_p4.c if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) { ctr 524 arch/x86/oprofile/op_model_p4.c counter_config[ctr].event); ctr 528 arch/x86/oprofile/op_model_p4.c ev = &(p4_events[counter_config[ctr].event - 1]); ctr 537 arch/x86/oprofile/op_model_p4.c ESCR_SET_USR_0(escr, counter_config[ctr].user); ctr 538 arch/x86/oprofile/op_model_p4.c ESCR_SET_OS_0(escr, counter_config[ctr].kernel); ctr 540 arch/x86/oprofile/op_model_p4.c ESCR_SET_USR_1(escr, counter_config[ctr].user); ctr 541 arch/x86/oprofile/op_model_p4.c ESCR_SET_OS_1(escr, counter_config[ctr].kernel); ctr 544 arch/x86/oprofile/op_model_p4.c ESCR_SET_EVENT_MASK(escr, counter_config[ctr].unit_mask); ctr 548 arch/x86/oprofile/op_model_p4.c rdmsr(p4_counters[VIRT_CTR(stag, ctr)].cccr_address, ctr 557 arch/x86/oprofile/op_model_p4.c wrmsr(p4_counters[VIRT_CTR(stag, ctr)].cccr_address, ctr 565 arch/x86/oprofile/op_model_p4.c counter_config[ctr].event, stag, ctr); ctr 618 arch/x86/oprofile/op_model_p4.c unsigned long ctr, low, high, stag, real; ctr 648 arch/x86/oprofile/op_model_p4.c rdmsr(p4_counters[real].counter_address, ctr, high); ctr 649 arch/x86/oprofile/op_model_p4.c if (CCCR_OVF_P(low) || !(ctr & OP_CTR_OVERFLOW)) { ctr 21 crypto/ccm.c struct crypto_skcipher_spawn ctr; ctr 27 crypto/ccm.c struct crypto_skcipher *ctr; ctr 92 crypto/ccm.c struct crypto_skcipher *ctr = ctx->ctr; ctr 96 crypto/ccm.c crypto_skcipher_clear_flags(ctr, CRYPTO_TFM_REQ_MASK); ctr 97 crypto/ccm.c crypto_skcipher_set_flags(ctr, crypto_aead_get_flags(aead) & ctr 99 crypto/ccm.c err = crypto_skcipher_setkey(ctr, key, keylen); ctr 100 crypto/ccm.c crypto_aead_set_flags(aead, crypto_skcipher_get_flags(ctr) & ctr 317 crypto/ccm.c skcipher_request_set_tfm(skreq, ctx->ctr); ctr 382 crypto/ccm.c skcipher_request_set_tfm(skreq, ctx->ctr); ctr 407 crypto/ccm.c struct crypto_skcipher *ctr; ctr 415 crypto/ccm.c ctr = crypto_spawn_skcipher(&ictx->ctr); ctr 416 crypto/ccm.c err = PTR_ERR(ctr); ctr 417 crypto/ccm.c if (IS_ERR(ctr)) ctr 421 crypto/ccm.c ctx->ctr = ctr; ctr 428 crypto/ccm.c max(crypto_ahash_reqsize(mac), crypto_skcipher_reqsize(ctr))); ctr 442 crypto/ccm.c crypto_free_skcipher(ctx->ctr); ctr 450 crypto/ccm.c crypto_drop_skcipher(&ctx->ctr); ctr 461 crypto/ccm.c struct skcipher_alg *ctr; ctr 498 crypto/ccm.c crypto_set_skcipher_spawn(&ictx->ctr, aead_crypto_instance(inst)); ctr 499 crypto/ccm.c err = crypto_grab_skcipher(&ictx->ctr, ctr_name, 0, ctr 505 crypto/ccm.c ctr = crypto_spawn_skcipher_alg(&ictx->ctr); ctr 509 crypto/ccm.c if (strncmp(ctr->base.cra_name, "ctr(", 4) != 0 || ctr 510 crypto/ccm.c crypto_skcipher_alg_ivsize(ctr) != 16 || ctr 511 crypto/ccm.c ctr->base.cra_blocksize != 1) ctr 515 crypto/ccm.c if (strcmp(ctr->base.cra_name + 4, mac->base.cra_name + 7) != 0) ctr 520 crypto/ccm.c "ccm(%s", ctr->base.cra_name + 4) >= CRYPTO_MAX_ALG_NAME) ctr 524 crypto/ccm.c "ccm_base(%s,%s)", ctr->base.cra_driver_name, ctr 528 crypto/ccm.c inst->alg.base.cra_flags = ctr->base.cra_flags & CRYPTO_ALG_ASYNC; ctr 530 crypto/ccm.c ctr->base.cra_priority) / 2; ctr 533 crypto/ccm.c ctr->base.cra_alignmask; ctr 535 crypto/ccm.c inst->alg.chunksize = crypto_skcipher_alg_chunksize(ctr); ctr 556 crypto/ccm.c crypto_drop_skcipher(&ictx->ctr); ctr 24 crypto/gcm.c struct crypto_skcipher_spawn ctr; ctr 29 crypto/gcm.c struct crypto_skcipher *ctr; ctr 98 crypto/gcm.c struct crypto_skcipher *ctr = ctx->ctr; ctr 110 crypto/gcm.c crypto_skcipher_clear_flags(ctr, CRYPTO_TFM_REQ_MASK); ctr 111 crypto/gcm.c crypto_skcipher_set_flags(ctr, crypto_aead_get_flags(aead) & ctr 113 crypto/gcm.c err = crypto_skcipher_setkey(ctr, key, keylen); ctr 114 crypto/gcm.c crypto_aead_set_flags(aead, crypto_skcipher_get_flags(ctr) & ctr 119 crypto/gcm.c data = kzalloc(sizeof(*data) + crypto_skcipher_reqsize(ctr), ctr 126 crypto/gcm.c skcipher_request_set_tfm(&data->req, ctr); ctr 194 crypto/gcm.c skcipher_request_set_tfm(skreq, ctx->ctr); ctr 532 crypto/gcm.c struct crypto_skcipher *ctr; ctr 541 crypto/gcm.c ctr = crypto_spawn_skcipher(&ictx->ctr); ctr 542 crypto/gcm.c err = PTR_ERR(ctr); ctr 543 crypto/gcm.c if (IS_ERR(ctr)) ctr 546 crypto/gcm.c ctx->ctr = ctr; ctr 554 crypto/gcm.c crypto_skcipher_reqsize(ctr), ctr 570 crypto/gcm.c crypto_free_skcipher(ctx->ctr); ctr 577 crypto/gcm.c crypto_drop_skcipher(&ctx->ctr); ctr 589 crypto/gcm.c struct skcipher_alg *ctr; ctr 628 crypto/gcm.c crypto_set_skcipher_spawn(&ctx->ctr, aead_crypto_instance(inst)); ctr 629 crypto/gcm.c err = crypto_grab_skcipher(&ctx->ctr, ctr_name, 0, ctr 635 crypto/gcm.c ctr = crypto_spawn_skcipher_alg(&ctx->ctr); ctr 639 crypto/gcm.c if (strncmp(ctr->base.cra_name, "ctr(", 4) != 0 || ctr 640 crypto/gcm.c crypto_skcipher_alg_ivsize(ctr) != 16 || ctr 641 crypto/gcm.c ctr->base.cra_blocksize != 1) ctr 646 crypto/gcm.c "gcm(%s", ctr->base.cra_name + 4) >= CRYPTO_MAX_ALG_NAME) ctr 650 crypto/gcm.c "gcm_base(%s,%s)", ctr->base.cra_driver_name, ctr 656 crypto/gcm.c ctr->base.cra_flags) & CRYPTO_ALG_ASYNC; ctr 658 crypto/gcm.c ctr->base.cra_priority) / 2; ctr 661 crypto/gcm.c ctr->base.cra_alignmask; ctr 664 crypto/gcm.c inst->alg.chunksize = crypto_skcipher_alg_chunksize(ctr); ctr 684 crypto/gcm.c crypto_drop_skcipher(&ctx->ctr); ctr 1016 drivers/crypto/atmel-aes.c u32 ctr; ctr 1028 drivers/crypto/atmel-aes.c ctr = be32_to_cpu(ctx->iv[3]); ctr 1031 drivers/crypto/atmel-aes.c start = ctr & 0xffff; ctr 1035 drivers/crypto/atmel-aes.c ctr |= 0xffff; ctr 1054 drivers/crypto/atmel-aes.c ctx->iv[3] = cpu_to_be32(ctr); ctr 141 drivers/crypto/caam/pdb.h struct ipsec_encap_ctr ctr; ctr 207 drivers/crypto/caam/pdb.h struct ipsec_decap_ctr ctr; ctr 140 drivers/crypto/mediatek/mtk-aes.c struct crypto_skcipher *ctr; ctr 441 drivers/crypto/mediatek/mtk-aes.c goto ctr; ctr 455 drivers/crypto/mediatek/mtk-aes.c ctr: ctr 576 drivers/crypto/mediatek/mtk-aes.c u32 start, end, ctr, blocks; ctr 588 drivers/crypto/mediatek/mtk-aes.c ctr = be32_to_cpu(cctx->iv[3]); ctr 591 drivers/crypto/mediatek/mtk-aes.c start = ctr; ctr 594 drivers/crypto/mediatek/mtk-aes.c ctr |= 0xffffffff; ctr 613 drivers/crypto/mediatek/mtk-aes.c cctx->iv[3] = cpu_to_be32(ctr); ctr 1017 drivers/crypto/mediatek/mtk-aes.c struct crypto_skcipher *ctr = gctx->ctr; ctr 1048 drivers/crypto/mediatek/mtk-aes.c crypto_skcipher_clear_flags(ctr, CRYPTO_TFM_REQ_MASK); ctr 1049 drivers/crypto/mediatek/mtk-aes.c crypto_skcipher_set_flags(ctr, crypto_aead_get_flags(aead) & ctr 1051 drivers/crypto/mediatek/mtk-aes.c err = crypto_skcipher_setkey(ctr, key, keylen); ctr 1052 drivers/crypto/mediatek/mtk-aes.c crypto_aead_set_flags(aead, crypto_skcipher_get_flags(ctr) & ctr 1057 drivers/crypto/mediatek/mtk-aes.c data = kzalloc(sizeof(*data) + crypto_skcipher_reqsize(ctr), ctr 1064 drivers/crypto/mediatek/mtk-aes.c skcipher_request_set_tfm(&data->req, ctr); ctr 1118 drivers/crypto/mediatek/mtk-aes.c ctx->ctr = crypto_alloc_skcipher("ctr(aes)", 0, ctr 1120 drivers/crypto/mediatek/mtk-aes.c if (IS_ERR(ctx->ctr)) { ctr 1122 drivers/crypto/mediatek/mtk-aes.c return PTR_ERR(ctx->ctr); ctr 1134 drivers/crypto/mediatek/mtk-aes.c crypto_free_skcipher(ctx->ctr); ctr 63 drivers/crypto/nx/nx-aes-ctr.c memcpy(nx_ctx->priv.ctr.nonce, ctr 124 drivers/crypto/nx/nx-aes-ctr.c memcpy(iv, nx_ctx->priv.ctr.nonce, CTR_RFC3686_IV_SIZE); ctr 138 drivers/crypto/nx/nx.h struct nx_ctr_priv ctr; ctr 183 drivers/crypto/omap-aes-gcm.c sk_req = skcipher_request_alloc(ctx->ctr, GFP_KERNEL); ctr 195 drivers/crypto/omap-aes-gcm.c ret = crypto_skcipher_setkey(ctx->ctr, (u8 *)ctx->key, ctx->keylen); ctr 651 drivers/crypto/omap-aes.c ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0); ctr 652 drivers/crypto/omap-aes.c if (IS_ERR(ctx->ctr)) { ctr 654 drivers/crypto/omap-aes.c return PTR_ERR(ctx->ctr); ctr 676 drivers/crypto/omap-aes.c if (ctx->ctr) ctr 677 drivers/crypto/omap-aes.c crypto_free_skcipher(ctx->ctr); ctr 101 drivers/crypto/omap-aes.h struct crypto_skcipher *ctr; ctr 77 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c u32 i, ctr = 0; ctr 84 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c ctr++; ctr 86 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c return ctr; ctr 91 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c u32 i, ctr = 0; ctr 98 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c ctr++; ctr 100 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c return ctr; ctr 82 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c u32 i, ctr = 0; ctr 89 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c ctr++; ctr 91 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c return ctr; ctr 96 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c u32 i, ctr = 0; ctr 103 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c ctr++; ctr 105 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c return ctr; ctr 875 drivers/crypto/qat/qat_common/qat_algs.c int ret, ctr = 0; ctr 898 drivers/crypto/qat/qat_common/qat_algs.c } while (ret == -EAGAIN && ctr++ < 10); ctr 917 drivers/crypto/qat/qat_common/qat_algs.c int ret, ctr = 0; ctr 943 drivers/crypto/qat/qat_common/qat_algs.c } while (ret == -EAGAIN && ctr++ < 10); ctr 1057 drivers/crypto/qat/qat_common/qat_algs.c int ret, ctr = 0; ctr 1089 drivers/crypto/qat/qat_common/qat_algs.c } while (ret == -EAGAIN && ctr++ < 10); ctr 1117 drivers/crypto/qat/qat_common/qat_algs.c int ret, ctr = 0; ctr 1149 drivers/crypto/qat/qat_common/qat_algs.c } while (ret == -EAGAIN && ctr++ < 10); ctr 266 drivers/crypto/qat/qat_common/qat_asym_algs.c int ret, ctr = 0; ctr 393 drivers/crypto/qat/qat_common/qat_asym_algs.c } while (ret == -EBUSY && ctr++ < 100); ctr 695 drivers/crypto/qat/qat_common/qat_asym_algs.c int ret, ctr = 0; ctr 787 drivers/crypto/qat/qat_common/qat_asym_algs.c } while (ret == -EBUSY && ctr++ < 100); ctr 829 drivers/crypto/qat/qat_common/qat_asym_algs.c int ret, ctr = 0; ctr 939 drivers/crypto/qat/qat_common/qat_asym_algs.c } while (ret == -EBUSY && ctr++ < 100); ctr 102 drivers/crypto/qat/qat_common/qat_crypto.c unsigned long ctr; ctr 108 drivers/crypto/qat/qat_common/qat_crypto.c ctr = atomic_read(&tmp_dev->ref_count); ctr 109 drivers/crypto/qat/qat_common/qat_crypto.c if (best > ctr) { ctr 111 drivers/crypto/qat/qat_common/qat_crypto.c best = ctr; ctr 133 drivers/crypto/qat/qat_common/qat_crypto.c unsigned long ctr; ctr 135 drivers/crypto/qat/qat_common/qat_crypto.c ctr = atomic_read(&tmp_inst->refctr); ctr 136 drivers/crypto/qat/qat_common/qat_crypto.c if (best > ctr) { ctr 138 drivers/crypto/qat/qat_common/qat_crypto.c best = ctr; ctr 84 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c uint32_t i, ctr = 0; ctr 91 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c ctr++; ctr 93 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c return ctr; ctr 98 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c uint32_t i, ctr = 0; ctr 105 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c ctr++; ctr 107 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c return ctr; ctr 1838 drivers/crypto/s5p-sss.c const u8 *key, const u8 *iv, const u8 *ctr, ctr 1847 drivers/crypto/s5p-sss.c if (ctr) ctr 1848 drivers/crypto/s5p-sss.c memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr, ctr 1932 drivers/crypto/s5p-sss.c u8 *iv, *ctr; ctr 1942 drivers/crypto/s5p-sss.c ctr = NULL; ctr 1946 drivers/crypto/s5p-sss.c ctr = req->info; ctr 1949 drivers/crypto/s5p-sss.c ctr = NULL; ctr 1981 drivers/crypto/s5p-sss.c s5p_set_aes(dev, dev->ctx->aes_key, iv, ctr, dev->ctx->keylen); ctr 189 drivers/crypto/virtio/virtio_crypto_mgr.c unsigned long ctr; ctr 198 drivers/crypto/virtio/virtio_crypto_mgr.c ctr = atomic_read(&tmp_dev->ref_count); ctr 199 drivers/crypto/virtio/virtio_crypto_mgr.c if (best > ctr) { ctr 201 drivers/crypto/virtio/virtio_crypto_mgr.c best = ctr; ctr 83 drivers/dma/zx_dma.c u32 ctr; ctr 163 drivers/dma/zx_dma.c writel_relaxed(hw->ctr, phy->base + REG_ZX_CTRL); ctr 415 drivers/dma/zx_dma.c ds->desc_hw[num].ctr = ccfg; ctr 541 drivers/dma/zx_dma.c ds->desc_hw[num - 1].ctr |= ZX_IRQ_ENABLE_ALL; ctr 598 drivers/dma/zx_dma.c ds->desc_hw[num - 1].ctr |= ZX_IRQ_ENABLE_ALL; ctr 14 drivers/gpu/drm/nouveau/include/nvif/if0003.h } ctr[4]; ctr 30 drivers/gpu/drm/nouveau/include/nvif/if0003.h __u32 ctr[4]; ctr 129 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfsrc_enable(struct nvkm_pm *pm, struct nvkm_perfctr *ctr) ctr 140 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c for (j = 0; j < 8 && ctr->source[i][j]; j++) { ctr 141 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c sig = nvkm_perfsig_find(pm, ctr->domain, ctr 142 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr->signal[i], &dom); ctr 146 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c src = nvkm_perfsrc_find(pm, sig, ctr->source[i][j]); ctr 155 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c value |= ((ctr->source[i][j] >> 32) << src->shift); ctr 168 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfsrc_disable(struct nvkm_pm *pm, struct nvkm_perfctr *ctr) ctr 179 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c for (j = 0; j < 8 && ctr->source[i][j]; j++) { ctr 180 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c sig = nvkm_perfsig_find(pm, ctr->domain, ctr 181 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr->signal[i], &dom); ctr 185 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c src = nvkm_perfsrc_find(pm, sig, ctr->source[i][j]); ctr 224 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (dom->ctr[i]) { ctr 225 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c dom->func->init(pm, dom, dom->ctr[i]); ctr 228 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfsrc_enable(pm, dom->ctr[i]); ctr 278 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (dom->ctr[i]) ctr 279 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c dom->func->read(pm, dom, dom->ctr[i]); ctr 286 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (dom->ctr[i]) ctr 287 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c args->v0.ctr[i] = dom->ctr[i]->ctr; ctr 317 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c struct nvkm_perfctr *ctr = dom->ctr[i]; ctr 318 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (ctr) { ctr 319 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfsrc_disable(pm, ctr); ctr 320 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (ctr->head.next) ctr 321 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c list_del(&ctr->head); ctr 323 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c kfree(ctr); ctr 334 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c struct nvkm_perfctr *ctr; ctr 340 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr = *pctr = kzalloc(sizeof(*ctr), GFP_KERNEL); ctr 341 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (!ctr) ctr 344 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr->domain = domain; ctr 345 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr->logic_op = logic_op; ctr 346 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr->slot = slot; ctr 349 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr->signal[i] = signal[i] - dom->signal; ctr 351 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c ctr->source[i][j] = source[i][j]; ctr 354 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c list_add_tail(&ctr->head, &dom->list); ctr 376 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c struct nvkm_perfctr *ctr[4] = {}; ctr 388 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c for (c = 0; c < ARRAY_SIZE(args->v0.ctr); c++) { ctr 392 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c for (s = 0; s < ARRAY_SIZE(args->v0.ctr[c].signal); s++) { ctr 394 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c args->v0.ctr[c].signal[s], ctr 396 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (args->v0.ctr[c].signal[s] && !sig[s]) ctr 400 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c src[s][m] = args->v0.ctr[c].source[s][m]; ctr 408 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c args->v0.ctr[c].logic_op, &ctr[c]); ctr 425 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c for (c = 0; c < ARRAY_SIZE(ctr); c++) ctr 426 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c dom->ctr[c] = ctr[c]; ctr 129 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c struct nvkm_perfctr *ctr) ctr 132 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c u32 log = ctr->logic_op; ctr 137 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c src |= ctr->signal[i] << (i * 8); ctr 141 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c nvkm_wr32(device, dom->addr + 0x040 + (ctr->slot * 0x08), src); ctr 142 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c nvkm_wr32(device, dom->addr + 0x044 + (ctr->slot * 0x08), log); ctr 147 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c struct nvkm_perfctr *ctr) ctr 151 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c switch (ctr->slot) { ctr 152 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 0: ctr->ctr = nvkm_rd32(device, dom->addr + 0x08c); break; ctr 153 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 1: ctr->ctr = nvkm_rd32(device, dom->addr + 0x088); break; ctr 154 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 2: ctr->ctr = nvkm_rd32(device, dom->addr + 0x080); break; ctr 155 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c case 3: ctr->ctr = nvkm_rd32(device, dom->addr + 0x090); break; ctr 28 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c struct nvkm_perfctr *ctr) ctr 31 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c u32 log = ctr->logic_op; ctr 36 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c src |= ctr->signal[i] << (i * 8); ctr 39 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c nvkm_wr32(device, 0x00a400 + dom->addr + (ctr->slot * 0x40), src); ctr 40 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c nvkm_wr32(device, 0x00a420 + dom->addr + (ctr->slot * 0x40), log); ctr 45 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c struct nvkm_perfctr *ctr) ctr 49 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c switch (ctr->slot) { ctr 50 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 0: ctr->ctr = nvkm_rd32(device, 0x00a700 + dom->addr); break; ctr 51 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 1: ctr->ctr = nvkm_rd32(device, 0x00a6c0 + dom->addr); break; ctr 52 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 2: ctr->ctr = nvkm_rd32(device, 0x00a680 + dom->addr); break; ctr 53 drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c case 3: ctr->ctr = nvkm_rd32(device, 0x00a740 + dom->addr); break; ctr 21 drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h u32 ctr; ctr 79 drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h struct nvkm_perfctr *ctr[4]; ctr 835 drivers/infiniband/hw/hfi1/sdma.c u8 ctr; ctr 905 drivers/infiniband/hw/hfi1/sdma.c for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++) ctr 906 drivers/infiniband/hw/hfi1/sdma.c map->sde[map->ctr + i] = map->sde[i]; ctr 915 drivers/infiniband/hw/hfi1/sdma.c for (i = 0; i < map->ctr; i++) { ctr 918 drivers/infiniband/hw/hfi1/sdma.c (map->ctr - i - 1) * sizeof(map->sde[0])); ctr 919 drivers/infiniband/hw/hfi1/sdma.c map->ctr--; ctr 920 drivers/infiniband/hw/hfi1/sdma.c pow = roundup_pow_of_two(map->ctr ? : 1); ctr 994 drivers/infiniband/hw/hfi1/sdma.c rht_node->map[vl]->ctr = 1; ctr 1009 drivers/infiniband/hw/hfi1/sdma.c int ctr, pow; ctr 1020 drivers/infiniband/hw/hfi1/sdma.c rht_node->map[vl]->ctr++; ctr 1021 drivers/infiniband/hw/hfi1/sdma.c ctr = rht_node->map[vl]->ctr; ctr 1022 drivers/infiniband/hw/hfi1/sdma.c rht_node->map[vl]->sde[ctr - 1] = sde; ctr 1023 drivers/infiniband/hw/hfi1/sdma.c pow = roundup_pow_of_two(ctr); ctr 1057 drivers/infiniband/hw/hfi1/sdma.c if (rht_node->map[i]->ctr) { ctr 1130 drivers/infiniband/hw/hfi1/sdma.c if (!rht_node->map[i] || !rht_node->map[i]->ctr) ctr 1135 drivers/infiniband/hw/hfi1/sdma.c for (j = 0; j < rht_node->map[i]->ctr; j++) { ctr 985 drivers/input/serio/i8042.c unsigned char ctr[2]; ctr 1000 drivers/input/serio/i8042.c if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { ctr 1005 drivers/input/serio/i8042.c } while (n < 2 || ctr[0] != ctr[1]); ctr 1007 drivers/input/serio/i8042.c i8042_initial_ctr = i8042_ctr = ctr[0]; ctr 79 drivers/isdn/capi/kcapi.c capi_ctr_get(struct capi_ctr *ctr) ctr 81 drivers/isdn/capi/kcapi.c if (!try_module_get(ctr->owner)) ctr 83 drivers/isdn/capi/kcapi.c return ctr; ctr 87 drivers/isdn/capi/kcapi.c capi_ctr_put(struct capi_ctr *ctr) ctr 89 drivers/isdn/capi/kcapi.c module_put(ctr->owner); ctr 160 drivers/isdn/capi/kcapi.c register_appl(struct capi_ctr *ctr, u16 applid, capi_register_params *rparam) ctr 162 drivers/isdn/capi/kcapi.c ctr = capi_ctr_get(ctr); ctr 164 drivers/isdn/capi/kcapi.c if (ctr) ctr 165 drivers/isdn/capi/kcapi.c ctr->register_appl(ctr, applid, rparam); ctr 172 drivers/isdn/capi/kcapi.c static void release_appl(struct capi_ctr *ctr, u16 applid) ctr 176 drivers/isdn/capi/kcapi.c ctr->release_appl(ctr, applid); ctr 177 drivers/isdn/capi/kcapi.c capi_ctr_put(ctr); ctr 183 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 191 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(contr); ctr 192 drivers/isdn/capi/kcapi.c if (ctr) { ctr 193 drivers/isdn/capi/kcapi.c if (ctr->state == CAPI_CTR_RUNNING) ctr 196 drivers/isdn/capi/kcapi.c ctr->state = CAPI_CTR_RUNNING; ctr 201 drivers/isdn/capi/kcapi.c register_appl(ctr, applid, &ap->rparam); ctr 204 drivers/isdn/capi/kcapi.c wake_up_interruptible_all(&ctr->state_wait_queue); ctr 212 drivers/isdn/capi/kcapi.c static void ctr_down(struct capi_ctr *ctr, int new_state) ctr 217 drivers/isdn/capi/kcapi.c if (ctr->state == CAPI_CTR_DETECTED || ctr->state == CAPI_CTR_DETACHED) ctr 220 drivers/isdn/capi/kcapi.c ctr->state = new_state; ctr 222 drivers/isdn/capi/kcapi.c memset(ctr->manu, 0, sizeof(ctr->manu)); ctr 223 drivers/isdn/capi/kcapi.c memset(&ctr->version, 0, sizeof(ctr->version)); ctr 224 drivers/isdn/capi/kcapi.c memset(&ctr->profile, 0, sizeof(ctr->profile)); ctr 225 drivers/isdn/capi/kcapi.c memset(ctr->serial, 0, sizeof(ctr->serial)); ctr 230 drivers/isdn/capi/kcapi.c capi_ctr_put(ctr); ctr 233 drivers/isdn/capi/kcapi.c wake_up_interruptible_all(&ctr->state_wait_queue); ctr 238 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 245 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(contr); ctr 246 drivers/isdn/capi/kcapi.c if (ctr) ctr 247 drivers/isdn/capi/kcapi.c ctr_down(ctr, CAPI_CTR_DETECTED); ctr 343 drivers/isdn/capi/kcapi.c void capi_ctr_handle_message(struct capi_ctr *ctr, u16 appl, ctr 351 drivers/isdn/capi/kcapi.c if (ctr->state != CAPI_CTR_RUNNING) { ctr 355 drivers/isdn/capi/kcapi.c ctr->cnr, cdb->buf); ctr 359 drivers/isdn/capi/kcapi.c ctr->cnr); ctr 366 drivers/isdn/capi/kcapi.c ctr->nrecvdatapkt++; ctr 367 drivers/isdn/capi/kcapi.c if (ctr->traceflag > 2) ctr 370 drivers/isdn/capi/kcapi.c ctr->nrecvctlpkt++; ctr 371 drivers/isdn/capi/kcapi.c if (ctr->traceflag) ctr 374 drivers/isdn/capi/kcapi.c showctl |= (ctr->traceflag & 1); ctr 378 drivers/isdn/capi/kcapi.c ctr->cnr, CAPIMSG_APPID(skb->data), ctr 385 drivers/isdn/capi/kcapi.c ctr->cnr, cdb->buf); ctr 389 drivers/isdn/capi/kcapi.c ctr->cnr, CAPIMSG_APPID(skb->data), ctr 430 drivers/isdn/capi/kcapi.c void capi_ctr_ready(struct capi_ctr *ctr) ctr 433 drivers/isdn/capi/kcapi.c ctr->cnr, ctr->name); ctr 435 drivers/isdn/capi/kcapi.c notify_push(CAPICTR_UP, ctr->cnr); ctr 448 drivers/isdn/capi/kcapi.c void capi_ctr_down(struct capi_ctr *ctr) ctr 450 drivers/isdn/capi/kcapi.c printk(KERN_NOTICE "kcapi: controller [%03d] down.\n", ctr->cnr); ctr 452 drivers/isdn/capi/kcapi.c notify_push(CAPICTR_DOWN, ctr->cnr); ctr 467 drivers/isdn/capi/kcapi.c void capi_ctr_suspend_output(struct capi_ctr *ctr) ctr 469 drivers/isdn/capi/kcapi.c if (!ctr->blocked) { ctr 471 drivers/isdn/capi/kcapi.c ctr->cnr); ctr 472 drivers/isdn/capi/kcapi.c ctr->blocked = 1; ctr 488 drivers/isdn/capi/kcapi.c void capi_ctr_resume_output(struct capi_ctr *ctr) ctr 490 drivers/isdn/capi/kcapi.c if (ctr->blocked) { ctr 492 drivers/isdn/capi/kcapi.c ctr->cnr); ctr 493 drivers/isdn/capi/kcapi.c ctr->blocked = 0; ctr 509 drivers/isdn/capi/kcapi.c int attach_capi_ctr(struct capi_ctr *ctr) ctr 524 drivers/isdn/capi/kcapi.c capi_controller[i] = ctr; ctr 526 drivers/isdn/capi/kcapi.c ctr->nrecvctlpkt = 0; ctr 527 drivers/isdn/capi/kcapi.c ctr->nrecvdatapkt = 0; ctr 528 drivers/isdn/capi/kcapi.c ctr->nsentctlpkt = 0; ctr 529 drivers/isdn/capi/kcapi.c ctr->nsentdatapkt = 0; ctr 530 drivers/isdn/capi/kcapi.c ctr->cnr = i + 1; ctr 531 drivers/isdn/capi/kcapi.c ctr->state = CAPI_CTR_DETECTED; ctr 532 drivers/isdn/capi/kcapi.c ctr->blocked = 0; ctr 533 drivers/isdn/capi/kcapi.c ctr->traceflag = showcapimsgs; ctr 534 drivers/isdn/capi/kcapi.c init_waitqueue_head(&ctr->state_wait_queue); ctr 536 drivers/isdn/capi/kcapi.c sprintf(ctr->procfn, "capi/controllers/%d", ctr->cnr); ctr 537 drivers/isdn/capi/kcapi.c ctr->procent = proc_create_single_data(ctr->procfn, 0, NULL, ctr 538 drivers/isdn/capi/kcapi.c ctr->proc_show, ctr); ctr 545 drivers/isdn/capi/kcapi.c ctr->cnr, ctr->name); ctr 560 drivers/isdn/capi/kcapi.c int detach_capi_ctr(struct capi_ctr *ctr) ctr 566 drivers/isdn/capi/kcapi.c ctr_down(ctr, CAPI_CTR_DETACHED); ctr 568 drivers/isdn/capi/kcapi.c if (capi_controller[ctr->cnr - 1] != ctr) { ctr 572 drivers/isdn/capi/kcapi.c capi_controller[ctr->cnr - 1] = NULL; ctr 575 drivers/isdn/capi/kcapi.c if (ctr->procent) ctr 576 drivers/isdn/capi/kcapi.c remove_proc_entry(ctr->procfn, NULL); ctr 579 drivers/isdn/capi/kcapi.c ctr->cnr, ctr->name); ctr 771 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 791 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(CAPIMSG_CONTROLLER(skb->data)); ctr 792 drivers/isdn/capi/kcapi.c if (!ctr || ctr->state != CAPI_CTR_RUNNING) ctr 794 drivers/isdn/capi/kcapi.c if (ctr->blocked) ctr 801 drivers/isdn/capi/kcapi.c ctr->nsentdatapkt++; ctr 803 drivers/isdn/capi/kcapi.c if (ctr->traceflag > 2) ctr 806 drivers/isdn/capi/kcapi.c ctr->nsentctlpkt++; ctr 808 drivers/isdn/capi/kcapi.c if (ctr->traceflag) ctr 811 drivers/isdn/capi/kcapi.c showctl |= (ctr->traceflag & 1); ctr 834 drivers/isdn/capi/kcapi.c return ctr->send_message(ctr, skb); ctr 851 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 861 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(contr); ctr 862 drivers/isdn/capi/kcapi.c if (ctr && ctr->state == CAPI_CTR_RUNNING) { ctr 863 drivers/isdn/capi/kcapi.c strncpy(buf, ctr->manu, CAPI_MANUFACTURER_LEN); ctr 886 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 896 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(contr); ctr 897 drivers/isdn/capi/kcapi.c if (ctr && ctr->state == CAPI_CTR_RUNNING) { ctr 898 drivers/isdn/capi/kcapi.c memcpy(verp, &ctr->version, sizeof(capi_version)); ctr 921 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 931 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(contr); ctr 932 drivers/isdn/capi/kcapi.c if (ctr && ctr->state == CAPI_CTR_RUNNING) { ctr 933 drivers/isdn/capi/kcapi.c strlcpy(serial, ctr->serial, CAPI_SERIAL_LEN); ctr 956 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 966 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(contr); ctr 967 drivers/isdn/capi/kcapi.c if (ctr && ctr->state == CAPI_CTR_RUNNING) { ctr 968 drivers/isdn/capi/kcapi.c memcpy(profp, &ctr->profile, sizeof(struct capi_profile)); ctr 980 drivers/isdn/capi/kcapi.c static int wait_on_ctr_state(struct capi_ctr *ctr, unsigned int state) ctr 985 drivers/isdn/capi/kcapi.c ctr = capi_ctr_get(ctr); ctr 986 drivers/isdn/capi/kcapi.c if (!ctr) ctr 990 drivers/isdn/capi/kcapi.c prepare_to_wait(&ctr->state_wait_queue, &wait, ctr 993 drivers/isdn/capi/kcapi.c if (ctr->state == state) ctr 995 drivers/isdn/capi/kcapi.c if (ctr->state == CAPI_CTR_DETACHED) { ctr 1008 drivers/isdn/capi/kcapi.c finish_wait(&ctr->state_wait_queue, &wait); ctr 1010 drivers/isdn/capi/kcapi.c capi_ctr_put(ctr); ctr 1022 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 1096 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(ldef.contr); ctr 1097 drivers/isdn/capi/kcapi.c if (!ctr) { ctr 1102 drivers/isdn/capi/kcapi.c if (ctr->load_firmware == NULL) { ctr 1126 drivers/isdn/capi/kcapi.c if (ctr->state != CAPI_CTR_DETECTED) { ctr 1131 drivers/isdn/capi/kcapi.c ctr->state = CAPI_CTR_LOADING; ctr 1133 drivers/isdn/capi/kcapi.c retval = ctr->load_firmware(ctr, &ldata); ctr 1135 drivers/isdn/capi/kcapi.c ctr->state = CAPI_CTR_DETECTED; ctr 1139 drivers/isdn/capi/kcapi.c retval = wait_on_ctr_state(ctr, CAPI_CTR_RUNNING); ctr 1153 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(rdef.contr); ctr 1154 drivers/isdn/capi/kcapi.c if (!ctr) { ctr 1159 drivers/isdn/capi/kcapi.c if (ctr->state == CAPI_CTR_DETECTED) ctr 1162 drivers/isdn/capi/kcapi.c if (ctr->reset_ctr == NULL) { ctr 1168 drivers/isdn/capi/kcapi.c ctr->reset_ctr(ctr); ctr 1170 drivers/isdn/capi/kcapi.c retval = wait_on_ctr_state(ctr, CAPI_CTR_DETECTED); ctr 1191 drivers/isdn/capi/kcapi.c struct capi_ctr *ctr; ctr 1212 drivers/isdn/capi/kcapi.c ctr = get_capi_ctr_by_nr(fdef.contr); ctr 1213 drivers/isdn/capi/kcapi.c if (ctr) { ctr 1214 drivers/isdn/capi/kcapi.c ctr->traceflag = fdef.flag; ctr 1216 drivers/isdn/capi/kcapi.c ctr->cnr, ctr->traceflag); ctr 66 drivers/isdn/capi/kcapi_proc.c struct capi_ctr *ctr = *(struct capi_ctr **) v; ctr 68 drivers/isdn/capi/kcapi_proc.c if (!ctr) ctr 72 drivers/isdn/capi/kcapi_proc.c ctr->cnr, ctr->driver_name, ctr 73 drivers/isdn/capi/kcapi_proc.c state2str(ctr->state), ctr 74 drivers/isdn/capi/kcapi_proc.c ctr->name, ctr 75 drivers/isdn/capi/kcapi_proc.c ctr->procinfo ? ctr->procinfo(ctr) : ""); ctr 82 drivers/isdn/capi/kcapi_proc.c struct capi_ctr *ctr = *(struct capi_ctr **) v; ctr 84 drivers/isdn/capi/kcapi_proc.c if (!ctr) ctr 88 drivers/isdn/capi/kcapi_proc.c ctr->cnr, ctr 89 drivers/isdn/capi/kcapi_proc.c ctr->nrecvctlpkt, ctr 90 drivers/isdn/capi/kcapi_proc.c ctr->nrecvdatapkt, ctr 91 drivers/isdn/capi/kcapi_proc.c ctr->nsentctlpkt, ctr 92 drivers/isdn/capi/kcapi_proc.c ctr->nsentdatapkt); ctr 3518 drivers/md/dm-cache-target.c .ctr = cache_ctr, ctr 2208 drivers/md/dm-clone-target.c .ctr = clone_ctr, ctr 90 drivers/md/dm-crypt.c int (*ctr)(struct crypt_config *cc, struct dm_target *ti, ctr 760 drivers/md/dm-crypt.c .ctr = crypt_iv_benbi_ctr, ctr 770 drivers/md/dm-crypt.c .ctr = crypt_iv_lmk_ctr, ctr 779 drivers/md/dm-crypt.c .ctr = crypt_iv_tcw_ctr, ctr 792 drivers/md/dm-crypt.c .ctr = crypt_iv_eboiv_ctr, ctr 2457 drivers/md/dm-crypt.c if (cc->iv_gen_ops && cc->iv_gen_ops->ctr) { ctr 2458 drivers/md/dm-crypt.c ret = cc->iv_gen_ops->ctr(cc, ti, ivopts); ctr 2970 drivers/md/dm-crypt.c .ctr = crypt_ctr, ctr 357 drivers/md/dm-delay.c .ctr = delay_ctr, ctr 491 drivers/md/dm-dust.c .ctr = dust_ctr, ctr 1696 drivers/md/dm-era-target.c .ctr = era_ctr, ctr 236 drivers/md/dm-exception-store.c r = type->ctr(tmp_store, (strlen(argv[0]) > 1 ? &argv[0][1] : NULL)); ctr 46 drivers/md/dm-exception-store.h int (*ctr) (struct dm_exception_store *store, char *options); ctr 496 drivers/md/dm-flakey.c .ctr = flakey_ctr, ctr 4190 drivers/md/dm-integrity.c .ctr = dm_integrity_ctr, ctr 226 drivers/md/dm-linear.c .ctr = linear_ctr, ctr 872 drivers/md/dm-log-userspace-base.c .ctr = userspace_ctr, ctr 1007 drivers/md/dm-log-writes.c .ctr = log_writes_ctr, ctr 167 drivers/md/dm-log.c if (type->ctr(log, ti, argc, argv)) { ctr 828 drivers/md/dm-log.c .ctr = core_ctr, ctr 846 drivers/md/dm-log.c .ctr = disk_ctr, ctr 2000 drivers/md/dm-mpath.c .ctr = multipath_ctr, ctr 4022 drivers/md/dm-raid.c .ctr = raid_ctr, ctr 1459 drivers/md/dm-raid1.c .ctr = mirror_ctr, ctr 926 drivers/md/dm-snap-persistent.c .ctr = persistent_ctr, ctr 941 drivers/md/dm-snap-persistent.c .ctr = persistent_ctr, ctr 106 drivers/md/dm-snap-transient.c .ctr = transient_ctr, ctr 118 drivers/md/dm-snap-transient.c .ctr = transient_ctr, ctr 2726 drivers/md/dm-snap.c .ctr = origin_ctr, ctr 2739 drivers/md/dm-snap.c .ctr = snapshot_ctr, ctr 2754 drivers/md/dm-snap.c .ctr = snapshot_ctr, ctr 492 drivers/md/dm-stripe.c .ctr = stripe_ctr, ctr 554 drivers/md/dm-switch.c .ctr = switch_ctr, ctr 785 drivers/md/dm-table.c r = tgt->type->ctr(tgt, argc, argv); ctr 154 drivers/md/dm-target.c .ctr = io_err_ctr, ctr 4127 drivers/md/dm-thin.c .ctr = pool_ctr, ctr 4506 drivers/md/dm-thin.c .ctr = thin_ctr, ctr 182 drivers/md/dm-unstripe.c .ctr = unstripe_ctr, ctr 1212 drivers/md/dm-verity-target.c .ctr = verity_ctr, ctr 2330 drivers/md/dm-writecache.c .ctr = writecache_ctr, ctr 63 drivers/md/dm-zero.c .ctr = zero_ctr, ctr 973 drivers/md/dm-zoned-target.c .ctr = dmz_ctr, ctr 22 drivers/media/pci/cobalt/cobalt-i2c.c u8 ctr; ctr 324 drivers/media/pci/cobalt/cobalt-i2c.c iowrite8(0, ®s->ctr); ctr 340 drivers/media/pci/cobalt/cobalt-i2c.c iowrite8(0, ®s->ctr); ctr 347 drivers/media/pci/cobalt/cobalt-i2c.c iowrite8(M00018_CTR_BITMAP_EN_MSK, ®s->ctr); ctr 549 drivers/media/platform/qcom/venus/vdec.c struct vdec_controls *ctr = &inst->controls.dec; ctr 554 drivers/media/platform/qcom/venus/vdec.c if (ctr->post_loop_deb_mode) { ctr 16 drivers/media/platform/qcom/venus/vdec_ctrls.c struct vdec_controls *ctr = &inst->controls.dec; ctr 20 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->post_loop_deb_mode = ctrl->val; ctr 25 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->profile = ctrl->val; ctr 29 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->level = ctrl->val; ctr 41 drivers/media/platform/qcom/venus/vdec_ctrls.c struct vdec_controls *ctr = &inst->controls.dec; ctr 54 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->profile = hprop.profile_level.profile; ctr 55 drivers/media/platform/qcom/venus/vdec_ctrls.c ctrl->val = ctr->profile; ctr 61 drivers/media/platform/qcom/venus/vdec_ctrls.c ctr->level = hprop.profile_level.level; ctr 62 drivers/media/platform/qcom/venus/vdec_ctrls.c ctrl->val = ctr->level; ctr 65 drivers/media/platform/qcom/venus/vdec_ctrls.c ctrl->val = ctr->post_loop_deb_mode; ctr 643 drivers/media/platform/qcom/venus/venc.c struct venc_controls *ctr = &inst->controls.enc; ctr 687 drivers/media/platform/qcom/venus/venc.c ctr->h264_entropy_mode); ctr 697 drivers/media/platform/qcom/venus/venc.c ctr->h264_loop_filter_mode); ctr 698 drivers/media/platform/qcom/venus/venc.c deblock.slice_alpha_offset = ctr->h264_loop_filter_alpha; ctr 699 drivers/media/platform/qcom/venus/venc.c deblock.slice_beta_offset = ctr->h264_loop_filter_beta; ctr 717 drivers/media/platform/qcom/venus/venc.c if (ctr->num_b_frames) { ctr 727 drivers/media/platform/qcom/venus/venc.c intra_period.pframes = ctr->num_p_frames; ctr 728 drivers/media/platform/qcom/venus/venc.c intra_period.bframes = ctr->num_b_frames; ctr 734 drivers/media/platform/qcom/venus/venc.c if (ctr->bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) ctr 744 drivers/media/platform/qcom/venus/venc.c if (!ctr->bitrate) ctr 747 drivers/media/platform/qcom/venus/venc.c bitrate = ctr->bitrate; ctr 757 drivers/media/platform/qcom/venus/venc.c if (!ctr->bitrate_peak) ctr 760 drivers/media/platform/qcom/venus/venc.c bitrate = ctr->bitrate_peak; ctr 771 drivers/media/platform/qcom/venus/venc.c quant.qp_i = ctr->h264_i_qp; ctr 772 drivers/media/platform/qcom/venus/venc.c quant.qp_p = ctr->h264_p_qp; ctr 773 drivers/media/platform/qcom/venus/venc.c quant.qp_b = ctr->h264_b_qp; ctr 780 drivers/media/platform/qcom/venus/venc.c quant_range.min_qp = ctr->h264_min_qp; ctr 781 drivers/media/platform/qcom/venus/venc.c quant_range.max_qp = ctr->h264_max_qp; ctr 789 drivers/media/platform/qcom/venus/venc.c ctr->profile.h264); ctr 791 drivers/media/platform/qcom/venus/venc.c ctr->level.h264); ctr 794 drivers/media/platform/qcom/venus/venc.c ctr->profile.vpx); ctr 798 drivers/media/platform/qcom/venus/venc.c ctr->profile.mpeg4); ctr 800 drivers/media/platform/qcom/venus/venc.c ctr->level.mpeg4); ctr 806 drivers/media/platform/qcom/venus/venc.c ctr->profile.hevc); ctr 808 drivers/media/platform/qcom/venus/venc.c ctr->level.hevc); ctr 72 drivers/media/platform/qcom/venus/venc_ctrls.c struct venc_controls *ctr = &inst->controls.enc; ctr 81 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->bitrate_mode = ctrl->val; ctr 84 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->bitrate = ctrl->val; ctr 88 drivers/media/platform/qcom/venus/venc_ctrls.c brate.bitrate = ctr->bitrate; ctr 100 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->bitrate_peak = ctrl->val; ctr 103 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_entropy_mode = ctrl->val; ctr 106 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.mpeg4 = ctrl->val; ctr 109 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.h264 = ctrl->val; ctr 112 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.hevc = ctrl->val; ctr 115 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->profile.vpx = ctrl->val; ctr 118 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->level.mpeg4 = ctrl->val; ctr 121 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->level.h264 = ctrl->val; ctr 124 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->level.hevc = ctrl->val; ctr 127 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_i_qp = ctrl->val; ctr 130 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_p_qp = ctrl->val; ctr 133 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_b_qp = ctrl->val; ctr 136 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_min_qp = ctrl->val; ctr 139 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_max_qp = ctrl->val; ctr 142 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->multi_slice_mode = ctrl->val; ctr 145 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->multi_slice_max_bytes = ctrl->val; ctr 148 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->multi_slice_max_mb = ctrl->val; ctr 151 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_loop_filter_alpha = ctrl->val; ctr 154 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_loop_filter_beta = ctrl->val; ctr 157 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_loop_filter_mode = ctrl->val; ctr 160 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->header_mode = ctrl->val; ctr 165 drivers/media/platform/qcom/venus/venc_ctrls.c ret = venc_calc_bpframes(ctrl->val, ctr->num_b_frames, &bframes, ctr 166 drivers/media/platform/qcom/venus/venc_ctrls.c &ctr->num_p_frames); ctr 170 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->gop_size = ctrl->val; ctr 173 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->h264_i_period = ctrl->val; ctr 176 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->vp8_min_qp = ctrl->val; ctr 179 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->vp8_max_qp = ctrl->val; ctr 182 drivers/media/platform/qcom/venus/venc_ctrls.c ret = venc_calc_bpframes(ctr->gop_size, ctrl->val, &bframes, ctr 183 drivers/media/platform/qcom/venus/venc_ctrls.c &ctr->num_p_frames); ctr 187 drivers/media/platform/qcom/venus/venc_ctrls.c ctr->num_b_frames = bframes; ctr 629 drivers/media/platform/rcar_drif.c u32 ctr; ctr 639 drivers/media/platform/rcar_drif.c ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR); ctr 640 drivers/media/platform/rcar_drif.c ctr |= (RCAR_DRIF_SICTR_RX_RISING_EDGE | ctr 642 drivers/media/platform/rcar_drif.c rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr); ctr 648 drivers/media/platform/rcar_drif.c ctr, ctr & RCAR_DRIF_SICTR_RX_EN, 7, 100000); ctr 662 drivers/media/platform/rcar_drif.c u32 ctr; ctr 667 drivers/media/platform/rcar_drif.c ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR); ctr 668 drivers/media/platform/rcar_drif.c ctr &= ~RCAR_DRIF_SICTR_RX_EN; ctr 669 drivers/media/platform/rcar_drif.c rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr); ctr 675 drivers/media/platform/rcar_drif.c ctr, !(ctr & RCAR_DRIF_SICTR_RX_EN), 7, 100000); ctr 709 drivers/media/platform/rcar_drif.c u32 ctr, str; ctr 714 drivers/media/platform/rcar_drif.c ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr, ctr 715 drivers/media/platform/rcar_drif.c !(ctr & RCAR_DRIF_SICTR_RESET), 7, 100000); ctr 1557 drivers/media/usb/dvb-usb/cxusb.c unsigned int ctr; ctr 1559 drivers/media/usb/dvb-usb/cxusb.c for (ctr = 0; ctr < as->desc.bNumEndpoints; ctr++) { ctr 1560 drivers/media/usb/dvb-usb/cxusb.c if ((as->endpoint[ctr].desc.bEndpointAddress & ctr 1564 drivers/media/usb/dvb-usb/cxusb.c if (as->endpoint[ctr].desc.bEndpointAddress & USB_DIR_IN && ctr 1565 drivers/media/usb/dvb-usb/cxusb.c ((as->endpoint[ctr].desc.bmAttributes & ctr 1577 drivers/media/usb/dvb-usb/cxusb.c unsigned int ctr; ctr 1585 drivers/media/usb/dvb-usb/cxusb.c for (ctr = 0; ctr < intf->num_altsetting; ctr++) { ctr 1586 drivers/media/usb/dvb-usb/cxusb.c if (intf->altsetting[ctr].desc.bAlternateSetting != 1) ctr 1589 drivers/media/usb/dvb-usb/cxusb.c if (cxusb_medion_check_altsetting(&intf->altsetting[ctr])) ctr 809 drivers/net/can/rcar/rcar_canfd.c u32 ctr; ctr 815 drivers/net/can/rcar/rcar_canfd.c ctr = RCANFD_GCTR_MEIE; ctr 817 drivers/net/can/rcar/rcar_canfd.c ctr |= RCANFD_GCTR_CFMPOFIE; ctr 819 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr); ctr 835 drivers/net/can/rcar/rcar_canfd.c u32 ctr, ch = priv->channel; ctr 841 drivers/net/can/rcar/rcar_canfd.c ctr = (RCANFD_CCTR_TAIE | ctr 846 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr); ctr 852 drivers/net/can/rcar/rcar_canfd.c u32 ctr, ch = priv->channel; ctr 854 drivers/net/can/rcar/rcar_canfd.c ctr = (RCANFD_CCTR_TAIE | ctr 859 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr); ctr 6810 drivers/net/ethernet/broadcom/bnx2.c #define GET_64BIT_NET_STATS64(ctr) \ ctr 6811 drivers/net/ethernet/broadcom/bnx2.c (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo)) ctr 6813 drivers/net/ethernet/broadcom/bnx2.c #define GET_64BIT_NET_STATS(ctr) \ ctr 6814 drivers/net/ethernet/broadcom/bnx2.c GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \ ctr 6815 drivers/net/ethernet/broadcom/bnx2.c GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr) ctr 6817 drivers/net/ethernet/broadcom/bnx2.c #define GET_32BIT_NET_STATS(ctr) \ ctr 6818 drivers/net/ethernet/broadcom/bnx2.c (unsigned long) (bp->stats_blk->ctr + \ ctr 6819 drivers/net/ethernet/broadcom/bnx2.c bp->temp_stats_blk->ctr) ctr 718 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c attr.ctr_id = action->ctr.ctr_id + ctr 719 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c action->ctr.offeset; ctr 1009 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c action->ctr.ctr_id = counter_id; ctr 748 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h } ctr; ctr 140 drivers/net/ethernet/mellanox/mlx5/core/wq.h static inline u16 mlx5_wq_cyc_ctr2ix(struct mlx5_wq_cyc *wq, u16 ctr) ctr 142 drivers/net/ethernet/mellanox/mlx5/core/wq.h return ctr & wq->fbc.sz_m1; ctr 173 drivers/net/ethernet/mellanox/mlx5/core/wq.h static inline u32 mlx5_cqwq_ctr2ix(struct mlx5_cqwq *wq, u32 ctr) ctr 175 drivers/net/ethernet/mellanox/mlx5/core/wq.h return ctr & wq->fbc.sz_m1; ctr 193 drivers/net/ethernet/mellanox/mlx5/core/wq.h static inline u32 mlx5_cqwq_get_ctr_wrap_cnt(struct mlx5_cqwq *wq, u32 ctr) ctr 195 drivers/net/ethernet/mellanox/mlx5/core/wq.h return ctr >> wq->fbc.log_sz; ctr 407 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c struct __ctrl *ctr = &entry->region.ctrl; ctr 412 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c addr = ctr->addr; ctr 413 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c no_ops = ctr->no_ops; ctr 418 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c if (!(ctr->opcode & (1 << k))) ctr 422 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c qlcnic_ind_wr(adapter, addr, ctr->val1); ctr 431 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c (data & ctr->val2)); ctr 436 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c (data | ctr->val3)); ctr 439 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c while (timeout <= ctr->timeout) { ctr 441 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c if ((data & ctr->val2) == ctr->val1) ctr 446 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c if (timeout > ctr->timeout) { ctr 453 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c temp = ctr->index_a; ctr 460 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c ctr->index_v, data); ctr 463 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c temp = ctr->index_v; ctr 469 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c data = ctr->val1; ctr 471 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c temp = ctr->index_a; ctr 480 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c ctr->index_v); ctr 481 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c data <<= ctr->shl_val; ctr 482 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c data >>= ctr->shr_val; ctr 483 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c if (ctr->val2) ctr 484 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c data &= ctr->val2; ctr 485 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c data |= ctr->val3; ctr 486 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c data += ctr->val1; ctr 488 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c ctr->index_v, data); ctr 496 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c addr += ctr->stride; ctr 268 drivers/net/wireless/ath/ath6kl/core.c u8 ctr; ctr 305 drivers/net/wireless/ath/ath6kl/core.c for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { ctr 306 drivers/net/wireless/ath/ath6kl/core.c spin_lock_init(&ar->sta_list[ctr].psq_lock); ctr 307 drivers/net/wireless/ath/ath6kl/core.c skb_queue_head_init(&ar->sta_list[ctr].psq); ctr 308 drivers/net/wireless/ath/ath6kl/core.c skb_queue_head_init(&ar->sta_list[ctr].apsdq); ctr 309 drivers/net/wireless/ath/ath6kl/core.c ar->sta_list[ctr].mgmt_psq_len = 0; ctr 310 drivers/net/wireless/ath/ath6kl/core.c INIT_LIST_HEAD(&ar->sta_list[ctr].mgmt_psq); ctr 311 drivers/net/wireless/ath/ath6kl/core.c ar->sta_list[ctr].aggr_conn = ctr 313 drivers/net/wireless/ath/ath6kl/core.c if (!ar->sta_list[ctr].aggr_conn) { ctr 50 drivers/net/wireless/ath/ath6kl/main.c u8 ctr; ctr 52 drivers/net/wireless/ath/ath6kl/main.c for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { ctr 53 drivers/net/wireless/ath/ath6kl/main.c if (ar->sta_list[ctr].aid == aid) { ctr 54 drivers/net/wireless/ath/ath6kl/main.c conn = &ar->sta_list[ctr]; ctr 218 drivers/net/wireless/ath/ath6kl/txrx.c u8 ctr = 0; ctr 221 drivers/net/wireless/ath/ath6kl/txrx.c for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { ctr 222 drivers/net/wireless/ath/ath6kl/txrx.c if (ar->sta_list[ctr].sta_flags & STA_PS_SLEEP) { ctr 14760 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u8 ctr; ctr 14776 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = len; ctr < 16; ctr++) { ctr 14778 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c t1_offset + ctr, 8, &end_event); ctr 14780 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c t2_offset + ctr, 8, &end_dly); ctr 15083 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c int ctr; ctr 15125 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 4; ctr++) ctr 15126 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = ctr 15127 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c nphy_def_lnagains[ctr] + ctr 15433 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c int ctr; ctr 16007 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 4; ctr++) ctr 16008 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = (hpf_code << 8) | 0x7c; ctr 16021 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 4; ctr++) ctr 16022 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = (hpf_code << 8) | 0x74; ctr 16027 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 21; ctr++) ctr 16028 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = 3 * ctr; ctr 16032 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 21; ctr++) ctr 16033 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = (u16) ctr; ctr 21882 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u8 ctr = 0, samp = 0; ctr 21909 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 4; ctr++) ctr 21910 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c rssi_buf[ctr] = 0; ctr 21921 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c ctr = 0; ctr 21922 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c tmp_buf[ctr++] = ((s8) ((rssi0 & 0x3f) << 2)) >> 2; ctr 21923 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c tmp_buf[ctr++] = ((s8) (((rssi0 >> 8) & 0x3f) << 2)) >> 2; ctr 21924 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c tmp_buf[ctr++] = ((s8) ((rssi1 & 0x3f) << 2)) >> 2; ctr 21925 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c tmp_buf[ctr++] = ((s8) (((rssi1 >> 8) & 0x3f) << 2)) >> 2; ctr 21927 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 4; ctr++) ctr 21928 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c rssi_buf[ctr] += tmp_buf[ctr]; ctr 22791 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u8 result_idx, ctr; ctr 22874 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < 2; ctr++) ctr 22875 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c poll_miniq[vcm][ctr] = ctr 22876 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c min(poll_results[vcm][ctr * 2 + 0], ctr 22877 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c poll_results[vcm][ctr * 2 + 1]); ctr 28193 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u8 ctr; ctr 28227 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (ctr = 0; ctr < tbl_len; ctr++) ctr 28228 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = 0; ctr 199 drivers/net/wireless/ti/wl1251/main.c u32 intr, ctr = WL1251_IRQ_LOOP_COUNT; ctr 292 drivers/net/wireless/ti/wl1251/main.c if (--ctr == 0) ctr 80 drivers/parport/parport_gsc.c s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0); ctr 85 drivers/parport/parport_gsc.c s->u.pc.ctr = parport_readb (CONTROL (p)); ctr 90 drivers/parport/parport_gsc.c parport_writeb (s->u.pc.ctr, CONTROL (p)); ctr 252 drivers/parport/parport_gsc.c priv->ctr = 0xc; ctr 53 drivers/parport/parport_gsc.h unsigned char ctr; ctr 96 drivers/parport/parport_gsc.h unsigned char ctr = priv->ctr; ctr 100 drivers/parport/parport_gsc.h mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); ctr 102 drivers/parport/parport_gsc.h ctr = (ctr & ~mask) ^ val; ctr 103 drivers/parport/parport_gsc.h ctr &= priv->ctr_writable; /* only write writable bits. */ ctr 104 drivers/parport/parport_gsc.h parport_writeb (ctr, CONTROL (p)); ctr 105 drivers/parport/parport_gsc.h priv->ctr = ctr; /* Update soft copy */ ctr 106 drivers/parport/parport_gsc.h return ctr; ctr 144 drivers/parport/parport_gsc.h return priv->ctr & rm; /* Use soft copy */ ctr 158 drivers/parport/parport_pc.c if (mode >= 2 && !(priv->ctr & 0x20)) { ctr 236 drivers/parport/parport_pc.c s->u.pc.ctr = 0xc; ctr 240 drivers/parport/parport_pc.c s->u.pc.ctr |= 0x10; ctr 249 drivers/parport/parport_pc.c s->u.pc.ctr = priv->ctr; ctr 258 drivers/parport/parport_pc.c register unsigned char c = s->u.pc.ctr & priv->ctr_writable; ctr 260 drivers/parport/parport_pc.c priv->ctr = c; ctr 2074 drivers/parport/parport_pc.c priv->ctr = 0xc; ctr 218 drivers/parport/parport_sunbpp.c s->u.pc.ctr = 0xc; ctr 224 drivers/parport/parport_sunbpp.c s->u.pc.ctr = parport_sunbpp_read_control(p); ctr 229 drivers/parport/parport_sunbpp.c parport_sunbpp_write_control(p, s->u.pc.ctr); ctr 275 drivers/perf/qcom_l2_pmu.c static inline void cluster_pmu_set_evcntcr(u32 ctr, u32 val) ctr 277 drivers/perf/qcom_l2_pmu.c set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val); ctr 280 drivers/perf/qcom_l2_pmu.c static inline void cluster_pmu_set_evtyper(u32 ctr, u32 val) ctr 282 drivers/perf/qcom_l2_pmu.c set_l2_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val); ctr 312 drivers/perf/qcom_l2_pmu.c static inline void cluster_pmu_set_evfilter_sys_mode(u32 ctr) ctr 318 drivers/perf/qcom_l2_pmu.c set_l2_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val); ctr 303 drivers/ps3/ps3-lpm.c u32 ps3_read_ctr(u32 cpu, u32 ctr) ctr 306 drivers/ps3/ps3-lpm.c u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1); ctr 311 drivers/ps3/ps3-lpm.c val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff); ctr 324 drivers/ps3/ps3-lpm.c void ps3_write_ctr(u32 cpu, u32 ctr, u32 val) ctr 329 drivers/ps3/ps3-lpm.c phys_ctr = ctr & (NR_PHYS_CTRS - 1); ctr 334 drivers/ps3/ps3-lpm.c if (ctr < NR_PHYS_CTRS) ctr 350 drivers/ps3/ps3-lpm.c u32 ps3_read_pm07_control(u32 cpu, u32 ctr) ctr 362 drivers/ps3/ps3-lpm.c void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val) ctr 368 drivers/ps3/ps3-lpm.c if (ctr >= NR_CTRS) { ctr 370 drivers/ps3/ps3-lpm.c __LINE__, ctr); ctr 374 drivers/ps3/ps3-lpm.c result = lv1_set_lpm_counter_control(lpm_priv->lpm_id, ctr, val, mask, ctr 378 drivers/ps3/ps3-lpm.c "failed: ctr %u, %s\n", __func__, __LINE__, ctr, ctr 2116 drivers/scsi/dc395x.c int ctr = 6000000; ctr 2124 drivers/scsi/dc395x.c 0x80) && --ctr); ctr 2125 drivers/scsi/dc395x.c if (ctr < 6000000 - 1) ctr 2128 drivers/scsi/dc395x.c if (!ctr) ctr 2260 drivers/scsi/dc395x.c int ctr = 6000000; ctr 2265 drivers/scsi/dc395x.c } while (!(TempDMAstatus & DMAXFERCOMP) && --ctr); ctr 2266 drivers/scsi/dc395x.c if (!ctr) ctr 91 drivers/staging/isdn/gigaset/capi.c struct capi_ctr ctr; ctr 323 drivers/staging/isdn/gigaset/capi.c static void send_data_b3_conf(struct cardstate *cs, struct capi_ctr *ctr, ctr 342 drivers/staging/isdn/gigaset/capi.c CAPIMSG_SETCONTROLLER(msg, ctr->cnr); ctr 350 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(ctr, appl, cskb); ctr 395 drivers/staging/isdn/gigaset/capi.c send_data_b3_conf(cs, &iif->ctr, ap->id, CAPIMSG_MSGID(req), ctr 446 drivers/staging/isdn/gigaset/capi.c CAPIMSG_SETCONTROLLER(skb->data, iif->ctr.cnr); ctr 457 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 515 drivers/staging/isdn/gigaset/capi.c iif->ctr.cnr | ((bcs->channel + 1) << 8)); ctr 665 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 692 drivers/staging/isdn/gigaset/capi.c iif->ctr.cnr | ((bcs->channel + 1) << 8)); ctr 706 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 728 drivers/staging/isdn/gigaset/capi.c iif->ctr.cnr | ((bcs->channel + 1) << 8) | (1 << 16)); ctr 741 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 788 drivers/staging/isdn/gigaset/capi.c iif->ctr.cnr | ((bcs->channel + 1) << 8)); ctr 810 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 902 drivers/staging/isdn/gigaset/capi.c iif->ctr.cnr | ((bcs->channel + 1) << 8) | (1 << 16)); ctr 914 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 950 drivers/staging/isdn/gigaset/capi.c strcpy(iif->ctr.manu, "Siemens"); ctr 952 drivers/staging/isdn/gigaset/capi.c iif->ctr.version.majorversion = 2; /* CAPI 2.0 */ ctr 953 drivers/staging/isdn/gigaset/capi.c iif->ctr.version.minorversion = 0; ctr 955 drivers/staging/isdn/gigaset/capi.c iif->ctr.version.majormanuversion = cs->fwver[0]; ctr 956 drivers/staging/isdn/gigaset/capi.c iif->ctr.version.minormanuversion = cs->fwver[1]; ctr 958 drivers/staging/isdn/gigaset/capi.c iif->ctr.profile.nbchannel = cs->channels; ctr 960 drivers/staging/isdn/gigaset/capi.c iif->ctr.profile.goptions = 0x11; ctr 962 drivers/staging/isdn/gigaset/capi.c iif->ctr.profile.support1 = 0x03; ctr 965 drivers/staging/isdn/gigaset/capi.c iif->ctr.profile.support2 = 0x02; ctr 967 drivers/staging/isdn/gigaset/capi.c iif->ctr.profile.support3 = 0x01; ctr 969 drivers/staging/isdn/gigaset/capi.c strcpy(iif->ctr.serial, "0"); ctr 970 drivers/staging/isdn/gigaset/capi.c capi_ctr_ready(&iif->ctr); ctr 983 drivers/staging/isdn/gigaset/capi.c capi_ctr_down(&iif->ctr); ctr 994 drivers/staging/isdn/gigaset/capi.c static void gigaset_register_appl(struct capi_ctr *ctr, u16 appl, ctr 998 drivers/staging/isdn/gigaset/capi.c = container_of(ctr, struct gigaset_capi_ctr, ctr); ctr 999 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = ctr->driverdata; ctr 1082 drivers/staging/isdn/gigaset/capi.c static void gigaset_release_appl(struct capi_ctr *ctr, u16 appl) ctr 1085 drivers/staging/isdn/gigaset/capi.c = container_of(ctr, struct gigaset_capi_ctr, ctr); ctr 1086 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1119 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1134 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 1144 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1272 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, cskb); ctr 1284 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1308 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1329 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1623 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1795 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1842 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1900 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, skb); ctr 1912 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 1990 drivers/staging/isdn/gigaset/capi.c capi_ctr_handle_message(&iif->ctr, ap->id, b3skb); ctr 2012 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 2065 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 2126 drivers/staging/isdn/gigaset/capi.c send_data_b3_conf(cs, &iif->ctr, ap->id, msgid, channel, handle, ctr 2139 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 2159 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 2178 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = iif->ctr.driverdata; ctr 2265 drivers/staging/isdn/gigaset/capi.c static u16 gigaset_send_message(struct capi_ctr *ctr, struct sk_buff *skb) ctr 2268 drivers/staging/isdn/gigaset/capi.c = container_of(ctr, struct gigaset_capi_ctr, ctr); ctr 2269 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = ctr->driverdata; ctr 2341 drivers/staging/isdn/gigaset/capi.c static char *gigaset_procinfo(struct capi_ctr *ctr) ctr 2343 drivers/staging/isdn/gigaset/capi.c return ctr->name; /* ToDo: more? */ ctr 2348 drivers/staging/isdn/gigaset/capi.c struct capi_ctr *ctr = m->private; ctr 2349 drivers/staging/isdn/gigaset/capi.c struct cardstate *cs = ctr->driverdata; ctr 2353 drivers/staging/isdn/gigaset/capi.c seq_printf(m, "%-16s %s\n", "name", ctr->name); ctr 2456 drivers/staging/isdn/gigaset/capi.c iif->ctr.owner = THIS_MODULE; ctr 2457 drivers/staging/isdn/gigaset/capi.c iif->ctr.driverdata = cs; ctr 2458 drivers/staging/isdn/gigaset/capi.c strncpy(iif->ctr.name, isdnid, sizeof(iif->ctr.name) - 1); ctr 2459 drivers/staging/isdn/gigaset/capi.c iif->ctr.driver_name = "gigaset"; ctr 2460 drivers/staging/isdn/gigaset/capi.c iif->ctr.load_firmware = NULL; ctr 2461 drivers/staging/isdn/gigaset/capi.c iif->ctr.reset_ctr = NULL; ctr 2462 drivers/staging/isdn/gigaset/capi.c iif->ctr.register_appl = gigaset_register_appl; ctr 2463 drivers/staging/isdn/gigaset/capi.c iif->ctr.release_appl = gigaset_release_appl; ctr 2464 drivers/staging/isdn/gigaset/capi.c iif->ctr.send_message = gigaset_send_message; ctr 2465 drivers/staging/isdn/gigaset/capi.c iif->ctr.procinfo = gigaset_procinfo; ctr 2466 drivers/staging/isdn/gigaset/capi.c iif->ctr.proc_show = gigaset_proc_show, ctr 2472 drivers/staging/isdn/gigaset/capi.c rc = attach_capi_ctr(&iif->ctr); ctr 2492 drivers/staging/isdn/gigaset/capi.c detach_capi_ctr(&iif->ctr); ctr 207 drivers/tty/serial/suncore.c static int ctr = 0; ctr 213 drivers/tty/serial/suncore.c if (mouse_got_break && ctr < 8) ctr 217 drivers/tty/serial/suncore.c ctr = 0; ctr 222 drivers/tty/serial/suncore.c ctr++; ctr 433 drivers/usb/misc/uss720.c s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0); ctr 445 drivers/usb/misc/uss720.c s->u.pc.ctr = priv->reg[1]; ctr 453 drivers/usb/misc/uss720.c set_1284_register(pp, 2, s->u.pc.ctr, GFP_ATOMIC); ctr 456 drivers/usb/misc/uss720.c priv->reg[1] = s->u.pc.ctr; ctr 252 drivers/usb/renesas_usbhs/fifo.c usbhs_bset(priv, fifo->ctr, BVAL, BVAL); ctr 259 drivers/usb/renesas_usbhs/fifo.c if (usbhs_read(priv, fifo->ctr) & FRDY) ctr 288 drivers/usb/renesas_usbhs/fifo.c usbhs_write(priv, fifo->ctr, BCLR); ctr 294 drivers/usb/renesas_usbhs/fifo.c return usbhs_read(priv, fifo->ctr) & DTLN_MASK; ctr 1433 drivers/usb/renesas_usbhs/fifo.c fifo->ctr = D##channel##FIFOCTR; \ ctr 1455 drivers/usb/renesas_usbhs/fifo.c fifo->ctr = CFIFOCTR; ctr 21 drivers/usb/renesas_usbhs/fifo.h u32 ctr; /* xFIFOCTR */ ctr 608 drivers/usb/serial/mos7720.c s->u.pc.ctr = DCR_INIT_VAL; ctr 624 drivers/usb/serial/mos7720.c s->u.pc.ctr = mos_parport->shadowDCR; ctr 97 drivers/watchdog/wdt.c static void wdt_ctr_mode(int ctr, int mode) ctr 99 drivers/watchdog/wdt.c ctr <<= 6; ctr 100 drivers/watchdog/wdt.c ctr |= 0x30; ctr 101 drivers/watchdog/wdt.c ctr |= (mode << 1); ctr 102 drivers/watchdog/wdt.c outb_p(ctr, WDT_CR); ctr 105 drivers/watchdog/wdt.c static void wdt_ctr_load(int ctr, int val) ctr 107 drivers/watchdog/wdt.c outb_p(val&0xFF, WDT_COUNT0+ctr); ctr 108 drivers/watchdog/wdt.c outb_p(val>>8, WDT_COUNT0+ctr); ctr 98 drivers/watchdog/wdt_pci.c static void wdtpci_ctr_mode(int ctr, int mode) ctr 100 drivers/watchdog/wdt_pci.c ctr <<= 6; ctr 101 drivers/watchdog/wdt_pci.c ctr |= 0x30; ctr 102 drivers/watchdog/wdt_pci.c ctr |= (mode << 1); ctr 103 drivers/watchdog/wdt_pci.c outb(ctr, WDT_CR); ctr 107 drivers/watchdog/wdt_pci.c static void wdtpci_ctr_load(int ctr, int val) ctr 109 drivers/watchdog/wdt_pci.c outb(val & 0xFF, WDT_COUNT0 + ctr); ctr 111 drivers/watchdog/wdt_pci.c outb(val >> 8, WDT_COUNT0 + ctr); ctr 825 fs/overlayfs/namei.c unsigned int ctr = 0; ctr 919 fs/overlayfs/namei.c if (upperdentry && !ctr && !ofs->noxattr && d.is_dir) { ctr 936 fs/overlayfs/namei.c if (upperdentry && !ctr && ctr 955 fs/overlayfs/namei.c if (d.metacopy && ctr) { ctr 960 fs/overlayfs/namei.c stack[ctr].dentry = this; ctr 961 fs/overlayfs/namei.c stack[ctr].layer = lower.layer; ctr 962 fs/overlayfs/namei.c ctr++; ctr 1007 fs/overlayfs/namei.c } else if (!d.is_dir && upperdentry && !ctr && origin_path) { ctr 1013 fs/overlayfs/namei.c ctr = 1; ctr 1032 fs/overlayfs/namei.c if (ctr && (!upperdentry || (!d.is_dir && !metacopy))) ctr 1045 fs/overlayfs/namei.c oe = ovl_alloc_entry(ctr); ctr 1050 fs/overlayfs/namei.c memcpy(oe->lowerstack, stack, sizeof(struct ovl_path) * ctr); ctr 1068 fs/overlayfs/namei.c if (upperdentry || ctr) { ctr 1073 fs/overlayfs/namei.c .numlower = ctr, ctr 1075 fs/overlayfs/namei.c .lowerdata = (ctr > 1 && !d.is_dir) ? ctr 1076 fs/overlayfs/namei.c stack[ctr - 1].dentry : NULL, ctr 1100 fs/overlayfs/namei.c for (i = 0; i < ctr; i++) ctr 837 fs/overlayfs/super.c unsigned int ctr = 1; ctr 845 fs/overlayfs/super.c ctr++; ctr 852 fs/overlayfs/super.c return ctr; ctr 173 include/linux/device-mapper.h dm_ctr_fn ctr; ctr 35 include/linux/dm-dirty-log.h int (*ctr)(struct dm_dirty_log *log, struct dm_target *ti, ctr 25 include/linux/parport.h unsigned int ctr; ctr 30 include/linux/parport.h unsigned int ctr; ctr 21 include/linux/parport_pc.h unsigned char ctr; ctr 100 include/linux/parport_pc.h dcr = i ? priv->ctr : inb (CONTROL (p)); ctr 133 include/linux/parport_pc.h unsigned char ctr = priv->ctr; ctr 137 include/linux/parport_pc.h mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); ctr 139 include/linux/parport_pc.h ctr = (ctr & ~mask) ^ val; ctr 140 include/linux/parport_pc.h ctr &= priv->ctr_writable; /* only write writable bits. */ ctr 141 include/linux/parport_pc.h outb (ctr, CONTROL (p)); ctr 142 include/linux/parport_pc.h priv->ctr = ctr; /* Update soft copy */ ctr 143 include/linux/parport_pc.h return ctr; ctr 181 include/linux/parport_pc.h return priv->ctr & rm; /* Use soft copy */ ctr 278 kernel/gcov/gcc_3_4.c struct gcov_ctr_info *ctr = &info->counts[i]; ctr 279 kernel/gcov/gcc_3_4.c size_t size = ctr->num * sizeof(gcov_type); ctr 281 kernel/gcov/gcc_3_4.c dup->counts[i].num = ctr->num; ctr 282 kernel/gcov/gcc_3_4.c dup->counts[i].merge = ctr->merge; ctr 286 kernel/gcov/gcc_3_4.c memcpy(dup->counts[i].values, ctr->values, size); ctr 16 net/dccp/ccids/lib/loss_interval.c static inline u8 LIH_INDEX(const u8 ctr) ctr 18 net/dccp/ccids/lib/loss_interval.c return LIH_SIZE - 1 - (ctr % LIH_SIZE); ctr 87 net/rds/stats.c struct rds_info_counter ctr; ctr 91 net/rds/stats.c BUG_ON(strlen(names[i]) >= sizeof(ctr.name)); ctr 92 net/rds/stats.c strncpy(ctr.name, names[i], sizeof(ctr.name) - 1); ctr 93 net/rds/stats.c ctr.name[sizeof(ctr.name) - 1] = '\0'; ctr 94 net/rds/stats.c ctr.value = values[i]; ctr 96 net/rds/stats.c rds_info_copy(iter, &ctr, sizeof(ctr)); ctr 87 sound/soc/fsl/fsl_audmix.c unsigned int *mask, unsigned int *ctr, ctr 102 sound/soc/fsl/fsl_audmix.c (*ctr) |= FSL_AUDMIX_CTR_MIXCLK(prm.clk - 1); ctr 161 sound/soc/fsl/fsl_audmix.c unsigned int reg_val, val, mask = 0, ctr = 0; ctr 195 sound/soc/fsl/fsl_audmix.c ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]); ctr 201 sound/soc/fsl/fsl_audmix.c ctr |= FSL_AUDMIX_CTR_OUTSRC(val); ctr 203 sound/soc/fsl/fsl_audmix.c return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr); ctr 248 sound/soc/fsl/fsl_audmix.c u32 mask = 0, ctr = 0; ctr 270 sound/soc/fsl/fsl_audmix.c ctr |= FSL_AUDMIX_CTR_OUTCKPOL(0); ctr 274 sound/soc/fsl/fsl_audmix.c ctr |= FSL_AUDMIX_CTR_OUTCKPOL(1); ctr 282 sound/soc/fsl/fsl_audmix.c return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr); ctr 39 tools/arch/powerpc/include/uapi/asm/kvm.h __u64 ctr; ctr 21 tools/perf/arch/powerpc/include/dwarf-regs-table.h REG_DWARFNUM_NAME(ctr, 109), ctr 68 tools/perf/arch/powerpc/util/dwarf-regs.c REG_DWARFNUM_NAME(ctr, 109), ctr 48 tools/perf/arch/powerpc/util/perf_regs.c SMPL_REG(ctr, PERF_REG_POWERPC_CTR), ctr 18 tools/perf/util/s390-cpumcf-kernel.h unsigned int ctr:16; /* 24-39 Number of stored counters */ ctr 34 tools/perf/util/s390-sample-raw.c return sizeof(*set) + set->ctr * sizeof(u64); ctr 59 tools/perf/util/s390-sample-raw.c ce.ctr = be16_to_cpu(cep->ctr); ctr 173 tools/perf/util/s390-sample-raw.c ce.ctr = be16_to_cpu(cep->ctr); ctr 183 tools/perf/util/s390-sample-raw.c " Counters:%d\n", offset, ce.set, ce.ctr); ctr 184 tools/perf/util/s390-sample-raw.c for (i = 0, p = (u64 *)(cep + 1); i < ce.ctr; ++i, ++p) {