ATHUB_BASE         38 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
ATHUB_BASE         38 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
ATHUB_BASE         38 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
ATHUB_BASE         38 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
ATHUB_BASE         38 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
ATHUB_BASE         38 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
ATHUB_BASE         39 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } },
ATHUB_BASE         37 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } },
ATHUB_BASE         39 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
ATHUB_BASE         39 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
ATHUB_BASE         46 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
ATHUB_BASE        133 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE ATHUB_BASE			= { { { { 0x00000C20, 0, 0, 0, 0 } },
ATHUB_BASE         39 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C20, 0, 0, 0, 0, 0 } },