ctl_val           192 arch/c6x/platforms/dscr.c 	u32 ctl_val, val;
ctl_val           214 arch/c6x/platforms/dscr.c 		ctl_val = ctl->enable << ctl_shift;
ctl_val           219 arch/c6x/platforms/dscr.c 		ctl_val = ctl->disable << ctl_shift;
ctl_val           229 arch/c6x/platforms/dscr.c 	val |= ctl_val;
ctl_val           241 arch/c6x/platforms/dscr.c 		ctl_val = stat->enable;
ctl_val           243 arch/c6x/platforms/dscr.c 		ctl_val = stat->disable;
ctl_val           249 arch/c6x/platforms/dscr.c 	} while (val != ctl_val);
ctl_val            85 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	u32 ctl_val = 0;
ctl_val           136 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	ctl_val =
ctl_val           139 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	*offset = cxd2880_convert2s_complement(ctl_val, 28);
ctl_val           143 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	u32 ctl_val = 0;
ctl_val           183 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	ctl_val =
ctl_val           186 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	*offset = cxd2880_convert2s_complement(ctl_val, 29);
ctl_val            98 drivers/mtd/spi-nor/aspeed-smc.c 	u32 ctl_val[smc_max];			/* control settings */
ctl_val           280 drivers/mtd/spi-nor/aspeed-smc.c 	u32 ctl = chip->ctl_val[smc_base];
ctl_val           300 drivers/mtd/spi-nor/aspeed-smc.c 	u32 ctl = chip->ctl_val[smc_read];
ctl_val           641 drivers/mtd/spi-nor/aspeed-smc.c 	chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B;
ctl_val           642 drivers/mtd/spi-nor/aspeed-smc.c 	chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B;
ctl_val           686 drivers/mtd/spi-nor/aspeed-smc.c 	chip->ctl_val[smc_base] = base_reg;
ctl_val           695 drivers/mtd/spi-nor/aspeed-smc.c 		chip->ctl_val[smc_read] = reg;
ctl_val           697 drivers/mtd/spi-nor/aspeed-smc.c 		chip->ctl_val[smc_read] = chip->ctl_val[smc_base] |
ctl_val           701 drivers/mtd/spi-nor/aspeed-smc.c 		chip->ctl_val[smc_read]);
ctl_val           720 drivers/mtd/spi-nor/aspeed-smc.c 	chip->ctl_val[smc_write] = chip->ctl_val[smc_base] |
ctl_val           725 drivers/mtd/spi-nor/aspeed-smc.c 		chip->ctl_val[smc_write]);
ctl_val           741 drivers/mtd/spi-nor/aspeed-smc.c 	chip->ctl_val[smc_read] |= cmd |
ctl_val           745 drivers/mtd/spi-nor/aspeed-smc.c 		chip->ctl_val[smc_read]);
ctl_val          2770 drivers/net/wireless/ath/ath5k/phy.c 	u8 *ctl_val = ee->ee_ctl;
ctl_val          2801 drivers/net/wireless/ath/ath5k/phy.c 		if (ctl_val[i] == ctl_mode) {
ctl_val           225 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	u32 ctl_val;
ctl_val           227 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val = ioread32(&ctl->bar_entry[bar].ctl);
ctl_val           228 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val &= ~NTB_CTRL_BAR_DIR_WIN_EN;
ctl_val           229 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
ctl_val           248 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	u32 ctl_val;
ctl_val           250 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val = ioread32(&ctl->bar_entry[bar].ctl);
ctl_val           251 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN;
ctl_val           253 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
ctl_val           915 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	u32 ctl_val;
ctl_val           923 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val = ioread32(&ctl->bar_entry[peer_bar].ctl);
ctl_val           924 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val &= 0xFF;
ctl_val           925 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val |= NTB_CTRL_BAR_LUT_WIN_EN;
ctl_val           926 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val |= ilog2(LUT_SIZE) << 8;
ctl_val           927 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	ctl_val |= (sndev->nr_lut_mw - 1) << 14;
ctl_val           928 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	iowrite32(ctl_val, &ctl->bar_entry[peer_bar].ctl);
ctl_val          1007 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 	u32 ctl_val;
ctl_val          1037 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 		ctl_val = ioread32(&ctl->bar_entry[bar].ctl);
ctl_val          1038 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 		ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN;
ctl_val          1040 drivers/ntb/hw/mscc/ntb_hw_switchtec.c 		iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
ctl_val           153 drivers/soc/qcom/spm.c 	u32 ctl_val;
ctl_val           157 drivers/soc/qcom/spm.c 	ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
ctl_val           158 drivers/soc/qcom/spm.c 	ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
ctl_val           159 drivers/soc/qcom/spm.c 	ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
ctl_val           160 drivers/soc/qcom/spm.c 	ctl_val |= SPM_CTL_EN;
ctl_val           161 drivers/soc/qcom/spm.c 	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
ctl_val            95 drivers/watchdog/bcm_kona_wdt.c 	int ctl_val, cur_val;
ctl_val           105 drivers/watchdog/bcm_kona_wdt.c 	ctl_val = secure_register_read(wdt, SECWDOG_CTRL_REG);
ctl_val           109 drivers/watchdog/bcm_kona_wdt.c 	if (ctl_val < 0 || cur_val < 0) {
ctl_val           114 drivers/watchdog/bcm_kona_wdt.c 		ctl = ctl_val & SECWDOG_COUNT_MASK;
ctl_val           115 drivers/watchdog/bcm_kona_wdt.c 		res = (ctl_val & SECWDOG_RES_MASK) >> SECWDOG_CLKS_SHIFT;