ctl_status_2 362 arch/mips/pci/pci-octeon.c union cvmx_pci_ctl_status_2 ctl_status_2; ctl_status_2 386 arch/mips/pci/pci-octeon.c ctl_status_2.u32 = 0; ctl_status_2 387 arch/mips/pci/pci-octeon.c ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set ctl_status_2 389 arch/mips/pci/pci-octeon.c ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ ctl_status_2 390 arch/mips/pci/pci-octeon.c ctl_status_2.s.bar2_enb = 1; ctl_status_2 391 arch/mips/pci/pci-octeon.c ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ ctl_status_2 392 arch/mips/pci/pci-octeon.c ctl_status_2.s.bar2_esx = 1; ctl_status_2 393 arch/mips/pci/pci-octeon.c ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ ctl_status_2 396 arch/mips/pci/pci-octeon.c ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; ctl_status_2 397 arch/mips/pci/pci-octeon.c ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ ctl_status_2 398 arch/mips/pci/pci-octeon.c ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ ctl_status_2 399 arch/mips/pci/pci-octeon.c ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ ctl_status_2 400 arch/mips/pci/pci-octeon.c ctl_status_2.s.bb1 = 1; /* BAR1 is big */ ctl_status_2 401 arch/mips/pci/pci-octeon.c ctl_status_2.s.bb0 = 1; /* BAR0 is big */ ctl_status_2 404 arch/mips/pci/pci-octeon.c octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); ctl_status_2 407 arch/mips/pci/pci-octeon.c ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); ctl_status_2 409 arch/mips/pci/pci-octeon.c ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", ctl_status_2 410 arch/mips/pci/pci-octeon.c ctl_status_2.s.ap_64ad ? "64" : "32"); ctl_status_2 435 arch/mips/pci/pci-octeon.c if (ctl_status_2.s.ap_pcix) {