ctl_cfg           687 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	const struct mdp5_ctl_block *ctl_cfg = &hw_cfg->ctl;
ctl_cfg           698 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	if (WARN_ON(ctl_cfg->count > MAX_CTL)) {
ctl_cfg           700 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 				ctl_cfg->count);
ctl_cfg           708 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	ctl_mgr->nctl = ctl_cfg->count;
ctl_cfg           709 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	ctl_mgr->flush_hw_mask = ctl_cfg->flush_hw_mask;
ctl_cfg           717 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		if (WARN_ON(!ctl_cfg->base[c])) {
ctl_cfg           725 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		ctl->reg_offset = ctl_cfg->base[c];