ctl2 207 drivers/gpu/drm/i915/display/dvo_tfp410.c u8 ctl2; ctl2 209 drivers/gpu/drm/i915/display/dvo_tfp410.c if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { ctl2 210 drivers/gpu/drm/i915/display/dvo_tfp410.c if (ctl2 & TFP410_CTL_2_RSEN) ctl2 1016 drivers/gpu/drm/i915/display/intel_panel.c u32 ctl, ctl2, freq; ctl2 1018 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(BLC_PWM_CTL2); ctl2 1019 drivers/gpu/drm/i915/display/intel_panel.c if (ctl2 & BLM_PWM_ENABLE) { ctl2 1021 drivers/gpu/drm/i915/display/intel_panel.c ctl2 &= ~BLM_PWM_ENABLE; ctl2 1022 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL2, ctl2); ctl2 1032 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = BLM_PIPE(pipe); ctl2 1034 drivers/gpu/drm/i915/display/intel_panel.c ctl2 |= BLM_COMBINATION_MODE; ctl2 1036 drivers/gpu/drm/i915/display/intel_panel.c ctl2 |= BLM_POLARITY_I965; ctl2 1037 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL2, ctl2); ctl2 1039 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); ctl2 1051 drivers/gpu/drm/i915/display/intel_panel.c u32 ctl, ctl2; ctl2 1053 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); ctl2 1054 drivers/gpu/drm/i915/display/intel_panel.c if (ctl2 & BLM_PWM_ENABLE) { ctl2 1056 drivers/gpu/drm/i915/display/intel_panel.c ctl2 &= ~BLM_PWM_ENABLE; ctl2 1057 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); ctl2 1066 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = 0; ctl2 1068 drivers/gpu/drm/i915/display/intel_panel.c ctl2 |= BLM_POLARITY_I965; ctl2 1069 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); ctl2 1071 drivers/gpu/drm/i915/display/intel_panel.c I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); ctl2 1698 drivers/gpu/drm/i915/display/intel_panel.c u32 ctl, ctl2, val; ctl2 1700 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(BLC_PWM_CTL2); ctl2 1701 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE; ctl2 1702 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; ctl2 1723 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE; ctl2 1732 drivers/gpu/drm/i915/display/intel_panel.c u32 ctl, ctl2, val; ctl2 1737 drivers/gpu/drm/i915/display/intel_panel.c ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); ctl2 1738 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; ctl2 1756 drivers/gpu/drm/i915/display/intel_panel.c panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE; ctl2 1752 drivers/hwmon/lm93.c u8 ctl2, ctl4; ctl2 1755 drivers/hwmon/lm93.c ctl2 = data->block9[nr][LM93_PWM_CTL2]; ctl2 1757 drivers/hwmon/lm93.c if (ctl2 & 0x01) /* show user commanded value if enabled */ ctl2 1760 drivers/hwmon/lm93.c rc = LM93_PWM_FROM_REG(ctl2 >> 4, (ctl4 & 0x07) ? ctl2 1771 drivers/hwmon/lm93.c u8 ctl2, ctl4; ctl2 1780 drivers/hwmon/lm93.c ctl2 = lm93_read_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2)); ctl2 1782 drivers/hwmon/lm93.c ctl2 = (ctl2 & 0x0f) | LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? ctl2 1785 drivers/hwmon/lm93.c data->pwm_override[nr] = LM93_PWM_FROM_REG(ctl2 >> 4, ctl2 1788 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2), ctl2); ctl2 1801 drivers/hwmon/lm93.c u8 ctl2; ctl2 1804 drivers/hwmon/lm93.c ctl2 = data->block9[nr][LM93_PWM_CTL2]; ctl2 1805 drivers/hwmon/lm93.c if (ctl2 & 0x01) /* manual override enabled ? */ ctl2 1806 drivers/hwmon/lm93.c rc = ((ctl2 & 0xF0) == 0xF0) ? 0 : 1; ctl2 1819 drivers/hwmon/lm93.c u8 ctl2; ctl2 1828 drivers/hwmon/lm93.c ctl2 = lm93_read_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2)); ctl2 1832 drivers/hwmon/lm93.c ctl2 |= 0xF1; /* enable manual override, set PWM to max */ ctl2 1835 drivers/hwmon/lm93.c ctl2 |= 0x01; /* enable manual override */ ctl2 1838 drivers/hwmon/lm93.c ctl2 &= ~0x01; /* disable manual override */ ctl2 1845 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2), ctl2); ctl2 66 drivers/mtd/nand/raw/cafe_nand.c uint32_t ctl2; ctl2 174 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); ctl2 176 drivers/mtd/nand/raw/cafe_nand.c cafe->ctl2 &= ~(1<<30); ctl2 243 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); ctl2 245 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); ctl2 298 drivers/mtd/nand/raw/cafe_nand.c WARN_ON(cafe->ctl2 & (1<<30)); ctl2 310 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); ctl2 314 drivers/mtd/nand/raw/cafe_nand.c cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); ctl2 544 drivers/mtd/nand/raw/cafe_nand.c cafe->ctl2 |= (1<<30); ctl2 617 drivers/mtd/nand/raw/cafe_nand.c cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */ ctl2 619 drivers/mtd/nand/raw/cafe_nand.c cafe->ctl2 |= BIT(29); /* 2KiB page size */ ctl2 301 drivers/mtd/spi-nor/aspeed-smc.c u32 ctl2 = ctl | CONTROL_COMMAND_MODE_USER | ctl2 304 drivers/mtd/spi-nor/aspeed-smc.c writel(ctl2, chip->ctl); /* stop user CE control */ ctl2 449 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c txd->ctl2 = 0; ctl2 459 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c txd->ctl2 |= (buff->mss << 16) | ctl2 478 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14); ctl2 482 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN; ctl2 505 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c txd->ctl2 = 0; ctl2 515 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c txd->ctl2 |= (buff->mss << 16); ctl2 523 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c txd->ctl2 |= (buff->len_l4 << 8) | ctl2 540 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14); ctl2 544 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN; ctl2 20 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */ ctl2 798 drivers/net/sungem_phy.c u16 ctl, ctl2; ctl2 828 drivers/net/sungem_phy.c ctl2 = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL); ctl2 829 drivers/net/sungem_phy.c ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX | ctl2 834 drivers/net/sungem_phy.c ctl2 |= (fd == DUPLEX_FULL) ? ctl2 837 drivers/net/sungem_phy.c sungem_phy_write(phy, MII_1000BASETCONTROL, ctl2); ctl2 279 drivers/net/wireless/ath/ath9k/mac.h u32 ctl2; ctl2 317 drivers/net/wireless/ath/ath9k/mac.h #define ds_ctl2 u.tx.ctl2 ctl2 370 drivers/net/wireless/mediatek/mt76/mt76x02_mac.c txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); ctl2 139 drivers/net/wireless/mediatek/mt76/mt76x02_mac.h u8 ctl2; ctl2 3538 drivers/pci/pci.c u32 cap, ctl2; ctl2 3582 drivers/pci/pci.c &ctl2); ctl2 3583 drivers/pci/pci.c if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) ctl2 83 drivers/pci/pcie/aspm.c u32 ctl2; /* value to be programmed in ctl2 */ ctl2 506 drivers/pci/pcie/aspm.c link->l1ss.ctl1 = link->l1ss.ctl2 = 0; ctl2 524 drivers/pci/pcie/aspm.c link->l1ss.ctl2 |= scale1 | (val1 << 3); ctl2 527 drivers/pci/pcie/aspm.c link->l1ss.ctl2 |= scale2 | (val2 << 3); ctl2 718 drivers/pci/pcie/aspm.c link->l1ss.ctl2); ctl2 720 drivers/pci/pcie/aspm.c link->l1ss.ctl2); ctl2 426 drivers/video/fbdev/arcfb.c unsigned char ctl2; ctl2 428 drivers/video/fbdev/arcfb.c ctl2 = ks108_readb_ctl2(info->par); ctl2 429 drivers/video/fbdev/arcfb.c if (copy_to_user(argp, &ctl2, sizeof(ctl2)))