DEGAMMA_CONTROL 2146 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); DEGAMMA_CONTROL 2147 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); DEGAMMA_CONTROL 2148 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); DEGAMMA_CONTROL 2182 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); DEGAMMA_CONTROL 2183 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); DEGAMMA_CONTROL 2184 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); DEGAMMA_CONTROL 228 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c REG_SET_3(DEGAMMA_CONTROL, 0, DEGAMMA_CONTROL 54 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(DEGAMMA_CONTROL, DCP, id) DEGAMMA_CONTROL 102 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \ DEGAMMA_CONTROL 103 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ DEGAMMA_CONTROL 104 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) DEGAMMA_CONTROL 219 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h uint32_t DEGAMMA_CONTROL;