ctch              126 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 		     struct intel_guc_ct_channel *ctch)
ctch              133 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	GEM_BUG_ON(ctch->vma);
ctch              163 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	ctch->vma = vma;
ctch              172 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 			intel_guc_ggtt_offset(guc, ctch->vma));
ctch              175 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
ctch              177 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 		ctch->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
ctch              178 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 		ctch->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
ctch              184 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	i915_vma_unpin_and_release(&ctch->vma, 0);
ctch              187 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 			ctch->owner, err);
ctch              192 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 		      struct intel_guc_ct_channel *ctch)
ctch              194 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	GEM_BUG_ON(ctch->enabled);
ctch              196 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
ctch              200 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 		       struct intel_guc_ct_channel *ctch)
ctch              206 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	GEM_BUG_ON(!ctch->vma);
ctch              208 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	GEM_BUG_ON(ctch->enabled);
ctch              211 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	base = intel_guc_ggtt_offset(guc, ctch->vma);
ctch              216 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
ctch              218 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 		guc_ct_buffer_desc_init(ctch->ctbs[i].desc,
ctch              221 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 					ctch->owner);
ctch              239 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	ctch->enabled = true;
ctch              245 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 					ctch->owner,
ctch              248 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
ctch              253 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 			 struct intel_guc_ct_channel *ctch)
ctch              255 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	GEM_BUG_ON(!ctch->enabled);
ctch              257 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	ctch->enabled = false;
ctch              260 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 					ctch->owner,
ctch              263 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 					ctch->owner,
ctch              267 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
ctch              270 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	return ++ctch->next_fence;
ctch              444 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 		     struct intel_guc_ct_channel *ctch,
ctch              451 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
ctch              458 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	GEM_BUG_ON(!ctch->enabled);
ctch              463 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	fence = ctch_get_next_fence(ctch);
ctch              518 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
ctch              524 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	ret = ctch_send(ct, ctch, action, len, response_buf, response_buf_size,
ctch              790 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
ctch              791 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_RECV];
ctch              795 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	if (!ctch->enabled)
ctch              838 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
ctch              841 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	err = ctch_init(guc, ctch);
ctch              844 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 			  ctch->owner, err);
ctch              848 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	GEM_BUG_ON(!ctch->vma);
ctch              862 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
ctch              864 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	ctch_fini(guc, ctch);
ctch              876 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
ctch              878 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	if (ctch->enabled)
ctch              881 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	return ctch_enable(guc, ctch);
ctch              891 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
ctch              893 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	if (!ctch->enabled)
ctch              896 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 	ctch_disable(guc, ctch);