csr_reg 40 arch/powerpc/boot/ugecon.c u32 *csr_reg = ug_io_base + EXI_CSR; csr_reg 47 arch/powerpc/boot/ugecon.c out_be32(csr_reg, csr); csr_reg 59 arch/powerpc/boot/ugecon.c out_be32(csr_reg, 0); csr_reg 47 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c u32 __iomem *csr_reg = ug_io_base + EXI_CSR; csr_reg 54 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c out_be32(csr_reg, csr); csr_reg 66 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c out_be32(csr_reg, 0); csr_reg 584 arch/sparc/kernel/pci_schizo.c unsigned long csr_reg, csr, csr_error_bits; csr_reg 588 arch/sparc/kernel/pci_schizo.c csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; csr_reg 589 arch/sparc/kernel/pci_schizo.c csr = upa_readq(csr_reg); csr_reg 599 arch/sparc/kernel/pci_schizo.c upa_writeq(csr, csr_reg); csr_reg 381 drivers/clk/clk-xgene.c void __iomem *csr_reg; csr_reg 398 drivers/clk/clk-xgene.c csr_reg = of_iomap(np, 0); csr_reg 399 drivers/clk/clk-xgene.c if (!csr_reg) { csr_reg 410 drivers/clk/clk-xgene.c csr_reg, XGENE_CLK_PMD_SHIFT, csr_reg 418 drivers/clk/clk-xgene.c if (csr_reg) csr_reg 419 drivers/clk/clk-xgene.c iounmap(csr_reg); csr_reg 425 drivers/clk/clk-xgene.c void __iomem *csr_reg; /* CSR for IP clock */ csr_reg 453 drivers/clk/clk-xgene.c if (pclk->param.csr_reg) { csr_reg 456 drivers/clk/clk-xgene.c data = xgene_clk_read(pclk->param.csr_reg + csr_reg 459 drivers/clk/clk-xgene.c xgene_clk_write(data, pclk->param.csr_reg + csr_reg 467 drivers/clk/clk-xgene.c data = xgene_clk_read(pclk->param.csr_reg + csr_reg 470 drivers/clk/clk-xgene.c xgene_clk_write(data, pclk->param.csr_reg + csr_reg 493 drivers/clk/clk-xgene.c if (pclk->param.csr_reg) { csr_reg 496 drivers/clk/clk-xgene.c data = xgene_clk_read(pclk->param.csr_reg + csr_reg 499 drivers/clk/clk-xgene.c xgene_clk_write(data, pclk->param.csr_reg + csr_reg 503 drivers/clk/clk-xgene.c data = xgene_clk_read(pclk->param.csr_reg + csr_reg 506 drivers/clk/clk-xgene.c xgene_clk_write(data, pclk->param.csr_reg + csr_reg 519 drivers/clk/clk-xgene.c if (pclk->param.csr_reg) { csr_reg 521 drivers/clk/clk-xgene.c data = xgene_clk_read(pclk->param.csr_reg + csr_reg 528 drivers/clk/clk-xgene.c if (!pclk->param.csr_reg) csr_reg 680 drivers/clk/clk-xgene.c parameters.csr_reg = NULL; csr_reg 700 drivers/clk/clk-xgene.c parameters.csr_reg = map_res; csr_reg 734 drivers/clk/clk-xgene.c if (parameters.csr_reg) csr_reg 735 drivers/clk/clk-xgene.c iounmap(parameters.csr_reg); csr_reg 143 drivers/net/wireless/intersil/orinoco/orinoco_plx.c u32 csr_reg; csr_reg 166 drivers/net/wireless/intersil/orinoco/orinoco_plx.c csr_reg = ioread32(card->bridge_io + PLX_INTCSR); csr_reg 167 drivers/net/wireless/intersil/orinoco/orinoco_plx.c if (!(csr_reg & PLX_INTCSR_INTEN)) { csr_reg 168 drivers/net/wireless/intersil/orinoco/orinoco_plx.c csr_reg |= PLX_INTCSR_INTEN; csr_reg 169 drivers/net/wireless/intersil/orinoco/orinoco_plx.c iowrite32(csr_reg, card->bridge_io + PLX_INTCSR); csr_reg 170 drivers/net/wireless/intersil/orinoco/orinoco_plx.c csr_reg = ioread32(card->bridge_io + PLX_INTCSR); csr_reg 171 drivers/net/wireless/intersil/orinoco/orinoco_plx.c if (!(csr_reg & PLX_INTCSR_INTEN)) {