csr_offset        198 drivers/crypto/qat/qat_common/adf_accel_devices.h #define ADF_CSR_WR(csr_base, csr_offset, val) \
csr_offset        199 drivers/crypto/qat/qat_common/adf_accel_devices.h 	__raw_writel(val, csr_base + csr_offset)
csr_offset        202 drivers/crypto/qat/qat_common/adf_accel_devices.h #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
csr_offset         91 drivers/firewire/core.h 	u32 (*read_csr)(struct fw_card *card, int csr_offset);
csr_offset         92 drivers/firewire/core.h 	void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
csr_offset       2612 drivers/firewire/ohci.c static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
csr_offset       2618 drivers/firewire/ohci.c 	switch (csr_offset) {
csr_offset       2663 drivers/firewire/ohci.c static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
csr_offset       2668 drivers/firewire/ohci.c 	switch (csr_offset) {
csr_offset        438 drivers/net/ethernet/cavium/thunder/thunder_bgx.c 	u64 csr_offset, cfg;
csr_offset        448 drivers/net/ethernet/cavium/thunder/thunder_bgx.c 		csr_offset = BGX_GMP_GMI_RXX_FRM_CTL;
csr_offset        450 drivers/net/ethernet/cavium/thunder/thunder_bgx.c 		csr_offset = BGX_SMUX_RX_FRM_CTL;
csr_offset        452 drivers/net/ethernet/cavium/thunder/thunder_bgx.c 	cfg = bgx_reg_read(bgx, lmacid, csr_offset);
csr_offset        458 drivers/net/ethernet/cavium/thunder/thunder_bgx.c 	bgx_reg_write(bgx, lmacid, csr_offset, cfg);