csr_core           85 drivers/ata/ahci_xgene.c 	void __iomem *csr_core;		/* Core CSR address of IP */
csr_core          669 drivers/ata/ahci_xgene.c 	writel(0, ctx->csr_core + INTSTATUSMASK);
csr_core          670 drivers/ata/ahci_xgene.c 	val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
csr_core          674 drivers/ata/ahci_xgene.c 	writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
csr_core          675 drivers/ata/ahci_xgene.c 	readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
csr_core          680 drivers/ata/ahci_xgene.c 	writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
csr_core          681 drivers/ata/ahci_xgene.c 	writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
csr_core          682 drivers/ata/ahci_xgene.c 	writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
csr_core          683 drivers/ata/ahci_xgene.c 	writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
csr_core          686 drivers/ata/ahci_xgene.c 	val = readl(ctx->csr_core + BUSCTLREG);
csr_core          689 drivers/ata/ahci_xgene.c 	writel(val, ctx->csr_core + BUSCTLREG);
csr_core          691 drivers/ata/ahci_xgene.c 	val = readl(ctx->csr_core + IOFMSTRWAUX);
csr_core          694 drivers/ata/ahci_xgene.c 	writel(val, ctx->csr_core + IOFMSTRWAUX);
csr_core          695 drivers/ata/ahci_xgene.c 	val = readl(ctx->csr_core + IOFMSTRWAUX);
csr_core          763 drivers/ata/ahci_xgene.c 	ctx->csr_core = devm_ioremap_resource(dev, res);
csr_core          764 drivers/ata/ahci_xgene.c 	if (IS_ERR(ctx->csr_core))
csr_core          765 drivers/ata/ahci_xgene.c 		return PTR_ERR(ctx->csr_core);
csr_core          820 drivers/ata/ahci_xgene.c 	dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,