csr_base 91 arch/ia64/kernel/acpi-ext.c acpi_status hp_acpi_csr_space(acpi_handle obj, u64 *csr_base, u64 *csr_length) csr_base 95 arch/ia64/kernel/acpi-ext.c status = hp_ccsr_locate(obj, csr_base, csr_length); csr_base 99 arch/ia64/kernel/acpi-ext.c return hp_crs_locate(obj, csr_base, csr_length); csr_base 282 drivers/ata/sata_fsl.c void __iomem *csr_base; csr_base 353 drivers/ata/sata_fsl.c void __iomem *csr_base = host_priv->csr_base; csr_base 356 drivers/ata/sata_fsl.c rx_watermark = ioread32(csr_base + TRANSCFG); csr_base 371 drivers/ata/sata_fsl.c void __iomem *csr_base = host_priv->csr_base; csr_base 380 drivers/ata/sata_fsl.c temp = ioread32(csr_base + TRANSCFG); csr_base 382 drivers/ata/sata_fsl.c iowrite32(temp | rx_watermark, csr_base + TRANSCFG); csr_base 577 drivers/ata/sata_fsl.c ioread32(COMMANDSTAT + host_priv->csr_base)); csr_base 655 drivers/ata/sata_fsl.c ioread32(host_priv->csr_base + COMMANDSTAT)); csr_base 1445 drivers/ata/sata_fsl.c void __iomem *csr_base = NULL; csr_base 1461 drivers/ata/sata_fsl.c csr_base = hcr_base + 0x140; csr_base 1464 drivers/ata/sata_fsl.c temp = ioread32(csr_base + TRANSCFG); csr_base 1466 drivers/ata/sata_fsl.c iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); csr_base 1469 drivers/ata/sata_fsl.c DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); csr_base 1479 drivers/ata/sata_fsl.c host_priv->csr_base = csr_base; csr_base 792 drivers/block/umem.c unsigned long csr_base; csr_base 809 drivers/block/umem.c csr_base = pci_resource_start(dev, 0); csr_base 811 drivers/block/umem.c if (!csr_base || !csr_len) csr_base 830 drivers/block/umem.c card->csr_remap = ioremap_nocache(csr_base, csr_len); csr_base 841 drivers/block/umem.c csr_base, card->csr_remap, csr_len); csr_base 80 drivers/char/hw_random/xgene-rng.c void __iomem *csr_base; csr_base 112 drivers/char/hw_random/xgene-rng.c writel(fro_val, ctx->csr_base + RNG_FRODETUNE); csr_base 113 drivers/char/hw_random/xgene-rng.c writel(0x00000000, ctx->csr_base + RNG_ALARMMASK); csr_base 114 drivers/char/hw_random/xgene-rng.c writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP); csr_base 115 drivers/char/hw_random/xgene-rng.c writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE); csr_base 122 drivers/char/hw_random/xgene-rng.c val = readl(ctx->csr_base + RNG_INTR_STS_ACK); csr_base 168 drivers/char/hw_random/xgene-rng.c frostopped = readl(ctx->csr_base + RNG_ALARMSTOP); csr_base 193 drivers/char/hw_random/xgene-rng.c frostopped = readl(ctx->csr_base + RNG_ALARMSTOP); csr_base 198 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_INTR_STS_ACK); csr_base 217 drivers/char/hw_random/xgene-rng.c val = readl(ctx->csr_base + RNG_INTR_STS_ACK); csr_base 232 drivers/char/hw_random/xgene-rng.c data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4); csr_base 235 drivers/char/hw_random/xgene-rng.c writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK); csr_base 244 drivers/char/hw_random/xgene-rng.c writel(0x00000000, ctx->csr_base + RNG_CONTROL); csr_base 248 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_CONFIG); csr_base 251 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_ALARMCNT); csr_base 262 drivers/char/hw_random/xgene-rng.c READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK); csr_base 272 drivers/char/hw_random/xgene-rng.c writel(val, ctx->csr_base + RNG_CONTROL); csr_base 282 drivers/char/hw_random/xgene-rng.c ctx->revision = readl(ctx->csr_base + RNG_EIP_REV); csr_base 290 drivers/char/hw_random/xgene-rng.c readl(ctx->csr_base + RNG_OPTIONS)); csr_base 328 drivers/char/hw_random/xgene-rng.c ctx->csr_base = devm_ioremap_resource(&pdev->dev, res); csr_base 329 drivers/char/hw_random/xgene-rng.c if (IS_ERR(ctx->csr_base)) csr_base 330 drivers/char/hw_random/xgene-rng.c return PTR_ERR(ctx->csr_base); csr_base 340 drivers/char/hw_random/xgene-rng.c ctx->csr_base, ctx->irq); csr_base 198 drivers/crypto/qat/qat_common/adf_accel_devices.h #define ADF_CSR_WR(csr_base, csr_offset, val) \ csr_base 199 drivers/crypto/qat/qat_common/adf_accel_devices.h __raw_writel(val, csr_base + csr_offset) csr_base 202 drivers/crypto/qat/qat_common/adf_accel_devices.h #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) csr_base 43 drivers/mtd/maps/intel_vr_nor.c void __iomem *csr_base; csr_base 103 drivers/mtd/maps/intel_vr_nor.c exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); csr_base 105 drivers/mtd/maps/intel_vr_nor.c writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); csr_base 111 drivers/mtd/maps/intel_vr_nor.c iounmap(p->csr_base); csr_base 136 drivers/mtd/maps/intel_vr_nor.c p->csr_base = ioremap_nocache(csr_phys, csr_len); csr_base 137 drivers/mtd/maps/intel_vr_nor.c if (!p->csr_base) csr_base 140 drivers/mtd/maps/intel_vr_nor.c exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); csr_base 164 drivers/mtd/maps/intel_vr_nor.c writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); csr_base 169 drivers/mtd/maps/intel_vr_nor.c iounmap(p->csr_base); csr_base 232 drivers/mtd/maps/intel_vr_nor.c exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); csr_base 234 drivers/mtd/maps/intel_vr_nor.c writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); csr_base 240 drivers/mtd/maps/intel_vr_nor.c iounmap(p->csr_base); csr_base 32 drivers/mtd/nand/raw/denali_pci.c resource_size_t csr_base, mem_base; csr_base 51 drivers/mtd/nand/raw/denali_pci.c csr_base = pci_resource_start(dev, 1); csr_base 54 drivers/mtd/nand/raw/denali_pci.c csr_base = pci_resource_start(dev, 0); csr_base 59 drivers/mtd/nand/raw/denali_pci.c mem_base = csr_base + csr_len; csr_base 77 drivers/mtd/nand/raw/denali_pci.c denali->reg = ioremap_nocache(csr_base, csr_len); csr_base 332 drivers/net/phy/mdio-xgene.c void __iomem *csr_base; csr_base 357 drivers/net/phy/mdio-xgene.c csr_base = devm_platform_ioremap_resource(pdev, 0); csr_base 358 drivers/net/phy/mdio-xgene.c if (IS_ERR(csr_base)) csr_base 359 drivers/net/phy/mdio-xgene.c return PTR_ERR(csr_base); csr_base 360 drivers/net/phy/mdio-xgene.c pdata->mac_csr_addr = csr_base; csr_base 361 drivers/net/phy/mdio-xgene.c pdata->mdio_csr_addr = csr_base + BLOCK_XG_MDIO_CSR_OFFSET; csr_base 362 drivers/net/phy/mdio-xgene.c pdata->diag_csr_addr = csr_base + BLOCK_DIAG_CSR_OFFSET; csr_base 95 drivers/net/wan/lmc/lmc_main.c static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size); csr_base 2024 drivers/net/wan/lmc/lmc_main.c static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/ csr_base 2028 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size; csr_base 2029 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size; csr_base 2030 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size; csr_base 2031 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size; csr_base 2032 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size; csr_base 2033 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_status = csr_base + 5 * csr_size; csr_base 2034 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_command = csr_base + 6 * csr_size; csr_base 2035 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size; csr_base 2036 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size; csr_base 2037 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size; csr_base 2038 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size; csr_base 2039 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size; csr_base 2040 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size; csr_base 2041 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size; csr_base 2042 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size; csr_base 2043 drivers/net/wan/lmc/lmc_main.c sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size; csr_base 68 drivers/pci/controller/pci-xgene.c void __iomem *csr_base; csr_base 77 drivers/pci/controller/pci-xgene.c return readl(port->csr_base + reg); csr_base 82 drivers/pci/controller/pci-xgene.c writel(val, port->csr_base + reg); csr_base 243 drivers/pci/controller/pci-xgene.c port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); csr_base 244 drivers/pci/controller/pci-xgene.c if (IS_ERR(port->csr_base)) csr_base 245 drivers/pci/controller/pci-xgene.c return PTR_ERR(port->csr_base); csr_base 354 drivers/pci/controller/pci-xgene.c port->csr_base = devm_pci_remap_cfg_resource(dev, res); csr_base 355 drivers/pci/controller/pci-xgene.c if (IS_ERR(port->csr_base)) csr_base 356 drivers/pci/controller/pci-xgene.c return PTR_ERR(port->csr_base); csr_base 34 drivers/pci/controller/pcie-altera-msi.c void __iomem *csr_base; csr_base 44 drivers/pci/controller/pcie-altera-msi.c writel_relaxed(value, msi->csr_base + reg); csr_base 49 drivers/pci/controller/pcie-altera-msi.c return readl_relaxed(msi->csr_base + reg); csr_base 232 drivers/pci/controller/pcie-altera-msi.c msi->csr_base = devm_ioremap_resource(&pdev->dev, res); csr_base 233 drivers/pci/controller/pcie-altera-msi.c if (IS_ERR(msi->csr_base)) { csr_base 235 drivers/pci/controller/pcie-altera-msi.c return PTR_ERR(msi->csr_base); csr_base 550 drivers/phy/phy-xgene.c static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg, csr_base 559 drivers/phy/phy-xgene.c writel(data, csr_base + indirect_data_reg); csr_base 560 drivers/phy/phy-xgene.c readl(csr_base + indirect_data_reg); /* Force a barrier */ csr_base 561 drivers/phy/phy-xgene.c writel(cmd, csr_base + indirect_cmd_reg); csr_base 562 drivers/phy/phy-xgene.c readl(csr_base + indirect_cmd_reg); /* Force a barrier */ csr_base 564 drivers/phy/phy-xgene.c val = readl(csr_base + indirect_cmd_reg); csr_base 569 drivers/phy/phy-xgene.c csr_base + indirect_cmd_reg, addr, data); csr_base 572 drivers/phy/phy-xgene.c static void sds_rd(void __iomem *csr_base, u32 indirect_cmd_reg, csr_base 581 drivers/phy/phy-xgene.c writel(cmd, csr_base + indirect_cmd_reg); csr_base 582 drivers/phy/phy-xgene.c readl(csr_base + indirect_cmd_reg); /* Force a barrier */ csr_base 584 drivers/phy/phy-xgene.c val = readl(csr_base + indirect_cmd_reg); csr_base 587 drivers/phy/phy-xgene.c *data = readl(csr_base + indirect_data_reg); csr_base 590 drivers/phy/phy-xgene.c csr_base + indirect_cmd_reg, addr, *data); csr_base 38 drivers/rtc/rtc-xgene.c void __iomem *csr_base; csr_base 48 drivers/rtc/rtc-xgene.c rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm); csr_base 60 drivers/rtc/rtc-xgene.c writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR); csr_base 61 drivers/rtc/rtc-xgene.c readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ csr_base 72 drivers/rtc/rtc-xgene.c alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE; csr_base 82 drivers/rtc/rtc-xgene.c ccr = readl(pdata->csr_base + RTC_CCR); csr_base 90 drivers/rtc/rtc-xgene.c writel(ccr, pdata->csr_base + RTC_CCR); csr_base 99 drivers/rtc/rtc-xgene.c return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0; csr_base 106 drivers/rtc/rtc-xgene.c writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR); csr_base 126 drivers/rtc/rtc-xgene.c if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT)) csr_base 130 drivers/rtc/rtc-xgene.c readl(pdata->csr_base + RTC_EOI); csr_base 151 drivers/rtc/rtc-xgene.c pdata->csr_base = devm_ioremap_resource(&pdev->dev, res); csr_base 152 drivers/rtc/rtc-xgene.c if (IS_ERR(pdata->csr_base)) csr_base 153 drivers/rtc/rtc-xgene.c return PTR_ERR(pdata->csr_base); csr_base 179 drivers/rtc/rtc-xgene.c writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);