csr_addr 266 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) csr_addr 268 arch/mips/include/asm/octeon/cvmx.h cvmx_write64(csr_addr, val); csr_addr 276 arch/mips/include/asm/octeon/cvmx.h if (((csr_addr >> 40) & 0x7ffff) == (0x118)) csr_addr 280 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val) csr_addr 282 arch/mips/include/asm/octeon/cvmx.h cvmx_write_csr((__force uint64_t)csr_addr, val); csr_addr 291 arch/mips/include/asm/octeon/cvmx.h static inline uint64_t cvmx_read_csr(uint64_t csr_addr) csr_addr 293 arch/mips/include/asm/octeon/cvmx.h uint64_t val = cvmx_read64(csr_addr); csr_addr 297 arch/mips/include/asm/octeon/cvmx.h static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr) csr_addr 299 arch/mips/include/asm/octeon/cvmx.h return cvmx_read_csr((__force uint64_t) csr_addr); csr_addr 308 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr) csr_addr 318 arch/mips/include/asm/octeon/cvmx.h addr.u64 = csr_addr; csr_addr 367 arch/mips/include/asm/octeon/cvmx.h static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr, csr_addr 373 arch/mips/include/asm/octeon/cvmx.h composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr; csr_addr 376 arch/mips/include/asm/octeon/cvmx.h if (((csr_addr >> 40) & 0x7ffff) == (0x118)) csr_addr 380 arch/mips/include/asm/octeon/cvmx.h static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr) csr_addr 384 arch/mips/include/asm/octeon/cvmx.h node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | csr_addr 314 arch/mips/include/asm/octeon/octeon-model.h static inline uint64_t cvmx_read_csr(uint64_t csr_addr); csr_addr 62 drivers/crypto/qat/qat_common/adf_hw_arbiter.c #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \ csr_addr 63 drivers/crypto/qat/qat_common/adf_hw_arbiter.c ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \ csr_addr 66 drivers/crypto/qat/qat_common/adf_hw_arbiter.c #define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \ csr_addr 67 drivers/crypto/qat/qat_common/adf_hw_arbiter.c ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \ csr_addr 70 drivers/crypto/qat/qat_common/adf_hw_arbiter.c #define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \ csr_addr 71 drivers/crypto/qat/qat_common/adf_hw_arbiter.c ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \ csr_addr 75 drivers/crypto/qat/qat_common/adf_hw_arbiter.c #define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \ csr_addr 76 drivers/crypto/qat/qat_common/adf_hw_arbiter.c ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \ csr_addr 82 drivers/crypto/qat/qat_common/adf_hw_arbiter.c void __iomem *csr = accel_dev->transport->banks[0].csr_addr; csr_addr 111 drivers/crypto/qat/qat_common/adf_hw_arbiter.c WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr, csr_addr 125 drivers/crypto/qat/qat_common/adf_hw_arbiter.c csr = accel_dev->transport->banks[0].csr_addr; csr_addr 98 drivers/crypto/qat/qat_common/adf_isr.c WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, 0); csr_addr 104 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask); csr_addr 105 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_COL_CTL(bank->csr_addr, bank->bank_number, csr_addr 114 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask); csr_addr 131 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_TAIL(ring->bank->csr_addr, ring->bank->bank_number, csr_addr 153 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_HEAD(ring->bank->csr_addr, csr_addr 163 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number, csr_addr 174 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number, csr_addr 210 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_BASE(ring->bank->csr_addr, ring->bank->bank_number, csr_addr 320 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_CONFIG(bank->csr_addr, bank->bank_number, csr_addr 322 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_BASE(bank->csr_addr, bank->bank_number, csr_addr 335 drivers/crypto/qat/qat_common/adf_transport.c empty_rings = READ_CSR_E_STAT(bank->csr_addr, bank->bank_number); csr_addr 350 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, csr_addr 387 drivers/crypto/qat/qat_common/adf_transport.c uint32_t bank_num, void __iomem *csr_addr) csr_addr 396 drivers/crypto/qat/qat_common/adf_transport.c bank->csr_addr = csr_addr; csr_addr 411 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_CONFIG(csr_addr, bank_num, i, 0); csr_addr 412 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_RING_BASE(csr_addr, bank_num, i, 0); csr_addr 437 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_FLAG(csr_addr, bank_num, ADF_BANK_INT_FLAG_CLEAR_MASK); csr_addr 438 drivers/crypto/qat/qat_common/adf_transport.c WRITE_CSR_INT_SRCSEL(csr_addr, bank_num); csr_addr 463 drivers/crypto/qat/qat_common/adf_transport.c void __iomem *csr_addr; csr_addr 484 drivers/crypto/qat/qat_common/adf_transport.c csr_addr = accel_dev->accel_pci_dev.pci_bars[i].virt_addr; csr_addr 492 drivers/crypto/qat/qat_common/adf_transport.c csr_addr); csr_addr 89 drivers/crypto/qat/qat_common/adf_transport_debug.c void __iomem *csr = ring->bank->csr_addr; csr_addr 209 drivers/crypto/qat/qat_common/adf_transport_debug.c void __iomem *csr = bank->csr_addr; csr_addr 78 drivers/crypto/qat/qat_common/adf_transport_internal.h void __iomem *csr_addr; csr_addr 227 drivers/crypto/qat/qat_common/adf_vf_isr.c WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, csr_addr 453 drivers/crypto/qat/qat_common/qat_hal.c void __iomem *csr_addr = csr_addr 462 drivers/crypto/qat/qat_common/qat_hal.c csr_val = ADF_CSR_RD(csr_addr, 0); csr_addr 466 drivers/crypto/qat/qat_common/qat_hal.c csr_val = ADF_CSR_RD(csr_addr, 0); csr_addr 468 drivers/crypto/qat/qat_common/qat_hal.c ADF_CSR_WR(csr_addr, 0, csr_val); csr_addr 472 drivers/crypto/qat/qat_common/qat_hal.c csr_val = ADF_CSR_RD(csr_addr, 0); csr_addr 1229 drivers/staging/octeon/octeon-stubs.h static inline uint64_t cvmx_read_csr(uint64_t csr_addr) csr_addr 1234 drivers/staging/octeon/octeon-stubs.h static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)