csi_rx_base       375 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(timing.clk_termen, q->csi_rx_base +
csi_rx_base       377 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(timing.clk_settle, q->csi_rx_base +
csi_rx_base       381 drivers/media/pci/intel/ipu3/ipu3-cio2.c 		writel(timing.dat_termen, q->csi_rx_base +
csi_rx_base       383 drivers/media/pci/intel/ipu3/ipu3-cio2.c 		writel(timing.dat_settle, q->csi_rx_base +
csi_rx_base       405 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	       q->csi_rx_base + CIO2_REG_CSIRX_STATUS_DLANE_HS);
csi_rx_base       407 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	       q->csi_rx_base + CIO2_REG_CSIRX_STATUS_DLANE_LP);
csi_rx_base       414 drivers/media/pci/intel/ipu3/ipu3-cio2.c 		writel(1, q->csi_rx_base + CIO2_REG_MIPIBE_SP_LUT_ENTRY(i));
csi_rx_base       419 drivers/media/pci/intel/ipu3/ipu3-cio2.c 		       q->csi_rx_base + CIO2_REG_MIPIBE_LP_LUT_ENTRY(i));
csi_rx_base       421 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	       q->csi_rx_base + CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD);
csi_rx_base       424 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_MASK);
csi_rx_base       425 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_ENABLE);
csi_rx_base       426 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_EDGE);
csi_rx_base       427 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE);
csi_rx_base       440 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	       q->csi_rx_base + CIO2_REG_MIPIBE_LP_LUT_ENTRY(ENTRY));
csi_rx_base       441 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_MIPIBE_COMP_FORMAT(sensor_vc));
csi_rx_base       442 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_MIPIBE_FORCE_RAW8);
csi_rx_base       445 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(lanes, q->csi_rx_base + CIO2_REG_CSIRX_NOF_ENABLED_LANES);
csi_rx_base       501 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_CLEAR);
csi_rx_base       507 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(1, q->csi_rx_base + CIO2_REG_MIPIBE_ENABLE);
csi_rx_base       508 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(1, q->csi_rx_base + CIO2_REG_CSIRX_ENABLE);
csi_rx_base       519 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_MASK);
csi_rx_base       520 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_ENABLE);
csi_rx_base       521 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_CSIRX_ENABLE);
csi_rx_base       522 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	writel(0, q->csi_rx_base + CIO2_REG_MIPIBE_ENABLE);
csi_rx_base       715 drivers/media/pci/intel/ipu3/ipu3-cio2.c 			void __iomem *const csi_rx_base =
csi_rx_base       730 drivers/media/pci/intel/ipu3/ipu3-cio2.c 				csi2_status = readl(csi_rx_base +
csi_rx_base       745 drivers/media/pci/intel/ipu3/ipu3-cio2.c 				       csi_rx_base + CIO2_REG_IRQCTRL_CLEAR);
csi_rx_base      1412 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	q->csi_rx_base = cio2->base + CIO2_REG_PIPE_BASE(q->csi2.port);
csi_rx_base       331 drivers/media/pci/intel/ipu3/ipu3-cio2.h 	void __iomem *csi_rx_base;