csels             398 drivers/edac/amd64_edac.c 		csbase		= pvt->csels[dct].csbases[csrow];
csels             399 drivers/edac/amd64_edac.c 		csmask		= pvt->csels[dct].csmasks[csrow];
csels             410 drivers/edac/amd64_edac.c 		csbase          = pvt->csels[dct].csbases[csrow];
csels             411 drivers/edac/amd64_edac.c 		csmask          = pvt->csels[dct].csmasks[csrow >> 1];
csels             426 drivers/edac/amd64_edac.c 		csbase		= pvt->csels[dct].csbases[csrow];
csels             427 drivers/edac/amd64_edac.c 		csmask		= pvt->csels[dct].csmasks[csrow >> 1];
csels             448 drivers/edac/amd64_edac.c 	for (i = 0; i < pvt->csels[dct].b_cnt; i++)
csels             451 drivers/edac/amd64_edac.c 	pvt->csels[dct].csbases[i]
csels             454 drivers/edac/amd64_edac.c 	for (i = 0; i < pvt->csels[dct].m_cnt; i++)
csels             764 drivers/edac/amd64_edac.c 		u32 dcsm = pvt->csels[chan].csmasks[0];
csels             934 drivers/edac/amd64_edac.c 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
csels             935 drivers/edac/amd64_edac.c 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
csels             937 drivers/edac/amd64_edac.c 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
csels             938 drivers/edac/amd64_edac.c 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
csels             943 drivers/edac/amd64_edac.c 			pvt->csels[umc].b_cnt = 4;
csels             944 drivers/edac/amd64_edac.c 			pvt->csels[umc].m_cnt = 2;
csels             948 drivers/edac/amd64_edac.c 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
csels             949 drivers/edac/amd64_edac.c 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
csels             968 drivers/edac/amd64_edac.c 			base = &pvt->csels[umc].csbases[cs];
csels             969 drivers/edac/amd64_edac.c 			base_sec = &pvt->csels[umc].csbases_sec[cs];
csels             987 drivers/edac/amd64_edac.c 			mask = &pvt->csels[umc].csmasks[cs];
csels             988 drivers/edac/amd64_edac.c 			mask_sec = &pvt->csels[umc].csmasks_sec[cs];
csels            1019 drivers/edac/amd64_edac.c 		u32 *base0 = &pvt->csels[0].csbases[cs];
csels            1020 drivers/edac/amd64_edac.c 		u32 *base1 = &pvt->csels[1].csbases[cs];
csels            1038 drivers/edac/amd64_edac.c 		u32 *mask0 = &pvt->csels[0].csmasks[cs];
csels            1039 drivers/edac/amd64_edac.c 		u32 *mask1 = &pvt->csels[1].csmasks[cs];
csels            1088 drivers/edac/amd64_edac.c 		dcsm = pvt->csels[0].csmasks[0];
csels            1542 drivers/edac/amd64_edac.c 	u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];
csels            1611 drivers/edac/amd64_edac.c 		addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];
csels            1613 drivers/edac/amd64_edac.c 		addr_mask_orig = pvt->csels[umc].csmasks[dimm];
csels            2169 drivers/edac/amd64_edac.c 	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
csels            2184 drivers/edac/amd64_edac.c 				 pvt->csels[1].csbases :
csels            2185 drivers/edac/amd64_edac.c 				 pvt->csels[0].csbases;
csels            2188 drivers/edac/amd64_edac.c 		dcsb = pvt->csels[1].csbases;
csels            3477 drivers/edac/amd64_edac.c 	layers[0].size = pvt->csels[0].b_cnt;
csels             174 drivers/edac/amd64_edac.h #define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
csels             175 drivers/edac/amd64_edac.h #define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
csels             364 drivers/edac/amd64_edac.h 	struct chip_select csels[NUM_CONTROLLERS];