csc_c33_c34 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c cur_csc_reg <= reg->csc_c33_c34; csc_c33_c34 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h uint32_t csc_c33_c34; csc_c33_c34 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); csc_c33_c34 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); csc_c33_c34 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); csc_c33_c34 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); csc_c33_c34 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); csc_c33_c34 495 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); csc_c33_c34 500 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); csc_c33_c34 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); csc_c33_c34 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); csc_c33_c34 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); csc_c33_c34 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);