csa                84 arch/arc/plat-eznps/include/plat/ctop.h 			u32 csa:22, dmsid:6, __reserved:3, cs:1;
csa                40 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ch0_cnt = ctx->csa.spu_chnlcnt_RW[0];
csa                41 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ch0_data = ctx->csa.spu_chnldata_RW[0];
csa                42 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ch1_data = ctx->csa.spu_chnldata_RW[1];
csa                43 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.spu_chnldata_RW[0] |= event;
csa                45 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnlcnt_RW[0] = 1;
csa                54 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa                55 arch/powerpc/platforms/cell/spufs/backing_ops.c 	mbox_stat = ctx->csa.prob.mb_stat_R;
csa                61 arch/powerpc/platforms/cell/spufs/backing_ops.c 		*data = ctx->csa.prob.pu_mb_R;
csa                62 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.prob.mb_stat_R &= ~(0x0000ff);
csa                63 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnlcnt_RW[28] = 1;
csa                67 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa                73 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.prob.mb_stat_R;
csa                83 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock_irq(&ctx->csa.register_lock);
csa                84 arch/powerpc/platforms/cell/spufs/backing_ops.c 	stat = ctx->csa.prob.mb_stat_R;
csa                95 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_stat_class2_RW &=
csa                97 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_mask_class2_RW |=
csa               105 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_stat_class2_RW &=
csa               107 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_mask_class2_RW |=
csa               111 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock_irq(&ctx->csa.register_lock);
csa               119 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               120 arch/powerpc/platforms/cell/spufs/backing_ops.c 	if (ctx->csa.prob.mb_stat_R & 0xff0000) {
csa               125 arch/powerpc/platforms/cell/spufs/backing_ops.c 		*data = ctx->csa.priv2.puint_mb_R;
csa               126 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.prob.mb_stat_R &= ~(0xff0000);
csa               127 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnlcnt_RW[30] = 1;
csa               132 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
csa               135 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               143 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               144 arch/powerpc/platforms/cell/spufs/backing_ops.c 	if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) {
csa               145 arch/powerpc/platforms/cell/spufs/backing_ops.c 		int slot = ctx->csa.spu_chnlcnt_RW[29];
csa               146 arch/powerpc/platforms/cell/spufs/backing_ops.c 		int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8;
csa               153 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_mailbox_data[slot] = data;
csa               154 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnlcnt_RW[29] = ++slot;
csa               155 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.prob.mb_stat_R &= ~(0x00ff00);
csa               156 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8);
csa               162 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.priv1.int_mask_class2_RW |=
csa               166 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               172 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.spu_chnldata_RW[3];
csa               177 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               178 arch/powerpc/platforms/cell/spufs/backing_ops.c 	if (ctx->csa.priv2.spu_cfg_RW & 0x1)
csa               179 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnldata_RW[3] |= data;
csa               181 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnldata_RW[3] = data;
csa               182 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.spu_chnlcnt_RW[3] = 1;
csa               184 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               189 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.spu_chnldata_RW[4];
csa               194 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               195 arch/powerpc/platforms/cell/spufs/backing_ops.c 	if (ctx->csa.priv2.spu_cfg_RW & 0x2)
csa               196 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnldata_RW[4] |= data;
csa               198 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.spu_chnldata_RW[4] = data;
csa               199 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.spu_chnlcnt_RW[4] = 1;
csa               201 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               208 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               209 arch/powerpc/platforms/cell/spufs/backing_ops.c 	tmp = ctx->csa.priv2.spu_cfg_RW;
csa               214 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.priv2.spu_cfg_RW = tmp;
csa               215 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               220 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0);
csa               227 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               228 arch/powerpc/platforms/cell/spufs/backing_ops.c 	tmp = ctx->csa.priv2.spu_cfg_RW;
csa               233 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.priv2.spu_cfg_RW = tmp;
csa               234 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               239 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0);
csa               244 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.prob.spu_npc_RW;
csa               249 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.prob.spu_npc_RW = val;
csa               254 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.prob.spu_status_R;
csa               259 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.lscsa->ls;
csa               264 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.priv2.spu_privcntl_RW = val;
csa               269 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.prob.spu_runcntl_RW;
csa               274 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               275 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.prob.spu_runcntl_RW = val;
csa               277 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.prob.spu_status_R &=
csa               283 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
csa               285 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
csa               287 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               297 arch/powerpc/platforms/cell/spufs/backing_ops.c 	struct spu_state *csa = &ctx->csa;
csa               300 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&csa->register_lock);
csa               301 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
csa               302 arch/powerpc/platforms/cell/spufs/backing_ops.c 	csa->priv1.mfc_sr1_RW = sr1;
csa               303 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&csa->register_lock);
csa               308 arch/powerpc/platforms/cell/spufs/backing_ops.c 	struct spu_state *csa = &ctx->csa;
csa               311 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&csa->register_lock);
csa               312 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
csa               313 arch/powerpc/platforms/cell/spufs/backing_ops.c 	csa->priv1.mfc_sr1_RW = sr1;
csa               314 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&csa->register_lock);
csa               320 arch/powerpc/platforms/cell/spufs/backing_ops.c 	struct spu_problem_collapsed *prob = &ctx->csa.prob;
csa               323 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               336 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.prob.dma_tagstatus_R &= mask;
csa               338 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               345 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.prob.dma_tagstatus_R;
csa               350 arch/powerpc/platforms/cell/spufs/backing_ops.c 	return ctx->csa.prob.dma_qstatus_R;
csa               358 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_lock(&ctx->csa.register_lock);
csa               361 arch/powerpc/platforms/cell/spufs/backing_ops.c 	spin_unlock(&ctx->csa.register_lock);
csa               368 arch/powerpc/platforms/cell/spufs/backing_ops.c 	ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
csa                35 arch/powerpc/platforms/cell/spufs/context.c 	if (spu_init_csa(&ctx->csa))
csa                77 arch/powerpc/platforms/cell/spufs/context.c 	spu_fini_csa(&ctx->csa);
csa                55 arch/powerpc/platforms/cell/spufs/fault.c 	unsigned long stat = ctx->csa.class_0_pending & CLASS0_INTR_MASK;
csa                61 arch/powerpc/platforms/cell/spufs/fault.c 		spufs_handle_event(ctx, ctx->csa.class_0_dar,
csa                65 arch/powerpc/platforms/cell/spufs/fault.c 		spufs_handle_event(ctx, ctx->csa.class_0_dar,
csa                69 arch/powerpc/platforms/cell/spufs/fault.c 		spufs_handle_event(ctx, ctx->csa.class_0_dar,
csa                72 arch/powerpc/platforms/cell/spufs/fault.c 	ctx->csa.class_0_pending = 0;
csa               102 arch/powerpc/platforms/cell/spufs/fault.c 	ea = ctx->csa.class_1_dar;
csa               103 arch/powerpc/platforms/cell/spufs/fault.c 	dsisr = ctx->csa.class_1_dsisr;
csa               141 arch/powerpc/platforms/cell/spufs/fault.c 	ctx->csa.class_1_dar = ctx->csa.class_1_dsisr = 0;
csa               242 arch/powerpc/platforms/cell/spufs/file.c 		pfn = vmalloc_to_pfn(ctx->csa.lscsa->ls + offset);
csa               465 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa               479 arch/powerpc/platforms/cell/spufs/file.c 	if (*pos >= sizeof(ctx->csa.lscsa->gprs))
csa               495 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa               523 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa               548 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa               979 arch/powerpc/platforms/cell/spufs/file.c 	if (ctx->csa.spu_chnlcnt_RW[3]) {
csa               980 arch/powerpc/platforms/cell/spufs/file.c 		data = ctx->csa.spu_chnldata_RW[3];
csa              1116 arch/powerpc/platforms/cell/spufs/file.c 	if (ctx->csa.spu_chnlcnt_RW[4]) {
csa              1117 arch/powerpc/platforms/cell/spufs/file.c 		data =  ctx->csa.spu_chnldata_RW[4];
csa              1787 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa              1801 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa              1816 arch/powerpc/platforms/cell/spufs/file.c 		ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
csa              1818 arch/powerpc/platforms/cell/spufs/file.c 		ctx->csa.priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
csa              1826 arch/powerpc/platforms/cell/spufs/file.c 	if (ctx->csa.priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING)
csa              1838 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa              1852 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa              1862 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_state *state = &ctx->csa;
csa              1875 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa              1889 arch/powerpc/platforms/cell/spufs/file.c 	struct spu_lscsa *lscsa = ctx->csa.lscsa;
csa              1928 arch/powerpc/platforms/cell/spufs/file.c 	return ctx->csa.priv2.spu_lslr_RW;
csa              1970 arch/powerpc/platforms/cell/spufs/file.c 	if (!(ctx->csa.prob.mb_stat_R & 0x0000ff))
csa              1973 arch/powerpc/platforms/cell/spufs/file.c 	data = ctx->csa.prob.pu_mb_R;
csa              1990 arch/powerpc/platforms/cell/spufs/file.c 	spin_lock(&ctx->csa.register_lock);
csa              1992 arch/powerpc/platforms/cell/spufs/file.c 	spin_unlock(&ctx->csa.register_lock);
csa              2010 arch/powerpc/platforms/cell/spufs/file.c 	if (!(ctx->csa.prob.mb_stat_R & 0xff0000))
csa              2013 arch/powerpc/platforms/cell/spufs/file.c 	data = ctx->csa.priv2.puint_mb_R;
csa              2030 arch/powerpc/platforms/cell/spufs/file.c 	spin_lock(&ctx->csa.register_lock);
csa              2032 arch/powerpc/platforms/cell/spufs/file.c 	spin_unlock(&ctx->csa.register_lock);
csa              2051 arch/powerpc/platforms/cell/spufs/file.c 	wbox_stat = ctx->csa.prob.mb_stat_R;
csa              2054 arch/powerpc/platforms/cell/spufs/file.c 		data[i] = ctx->csa.spu_mailbox_data[i];
csa              2073 arch/powerpc/platforms/cell/spufs/file.c 	spin_lock(&ctx->csa.register_lock);
csa              2075 arch/powerpc/platforms/cell/spufs/file.c 	spin_unlock(&ctx->csa.register_lock);
csa              2094 arch/powerpc/platforms/cell/spufs/file.c 	info.dma_info_type = ctx->csa.priv2.spu_tag_status_query_RW;
csa              2095 arch/powerpc/platforms/cell/spufs/file.c 	info.dma_info_mask = ctx->csa.lscsa->tag_mask.slot[0];
csa              2096 arch/powerpc/platforms/cell/spufs/file.c 	info.dma_info_status = ctx->csa.spu_chnldata_RW[24];
csa              2097 arch/powerpc/platforms/cell/spufs/file.c 	info.dma_info_stall_and_notify = ctx->csa.spu_chnldata_RW[25];
csa              2098 arch/powerpc/platforms/cell/spufs/file.c 	info.dma_info_atomic_command_status = ctx->csa.spu_chnldata_RW[27];
csa              2101 arch/powerpc/platforms/cell/spufs/file.c 		spuqp = &ctx->csa.priv2.spuq[i];
csa              2125 arch/powerpc/platforms/cell/spufs/file.c 	spin_lock(&ctx->csa.register_lock);
csa              2127 arch/powerpc/platforms/cell/spufs/file.c 	spin_unlock(&ctx->csa.register_lock);
csa              2153 arch/powerpc/platforms/cell/spufs/file.c 	info.proxydma_info_type = ctx->csa.prob.dma_querytype_RW;
csa              2154 arch/powerpc/platforms/cell/spufs/file.c 	info.proxydma_info_mask = ctx->csa.prob.dma_querymask_RW;
csa              2155 arch/powerpc/platforms/cell/spufs/file.c 	info.proxydma_info_status = ctx->csa.prob.dma_tagstatus_R;
csa              2158 arch/powerpc/platforms/cell/spufs/file.c 		puqp = &ctx->csa.priv2.puq[i];
csa              2179 arch/powerpc/platforms/cell/spufs/file.c 	spin_lock(&ctx->csa.register_lock);
csa              2181 arch/powerpc/platforms/cell/spufs/file.c 	spin_unlock(&ctx->csa.register_lock);
csa              2518 arch/powerpc/platforms/cell/spufs/file.c 		struct spu_state *csa = &ctx->csa;
csa              2520 arch/powerpc/platforms/cell/spufs/file.c 		mfc_control_RW = csa->priv2.mfc_control_RW;
csa              2532 arch/powerpc/platforms/cell/spufs/file.c 		ctx->csa.class_0_pending,
csa              2533 arch/powerpc/platforms/cell/spufs/file.c 		ctx->csa.class_0_dar,
csa              2534 arch/powerpc/platforms/cell/spufs/file.c 		ctx->csa.class_1_dsisr,
csa                21 arch/powerpc/platforms/cell/spufs/lscsa_alloc.c int spu_alloc_lscsa(struct spu_state *csa)
csa                29 arch/powerpc/platforms/cell/spufs/lscsa_alloc.c 	csa->lscsa = lscsa;
csa                38 arch/powerpc/platforms/cell/spufs/lscsa_alloc.c void spu_free_lscsa(struct spu_state *csa)
csa                43 arch/powerpc/platforms/cell/spufs/lscsa_alloc.c 	if (csa->lscsa == NULL)
csa                46 arch/powerpc/platforms/cell/spufs/lscsa_alloc.c 	for (p = csa->lscsa->ls; p < csa->lscsa->ls + LS_SIZE; p += PAGE_SIZE)
csa                49 arch/powerpc/platforms/cell/spufs/lscsa_alloc.c 	vfree(csa->lscsa);
csa                30 arch/powerpc/platforms/cell/spufs/run.c 			ctx->csa.class_0_pending = spu->class_0_pending;
csa                31 arch/powerpc/platforms/cell/spufs/run.c 			ctx->csa.class_0_dar = spu->class_0_dar;
csa                34 arch/powerpc/platforms/cell/spufs/run.c 			ctx->csa.class_1_dsisr = spu->class_1_dsisr;
csa                35 arch/powerpc/platforms/cell/spufs/run.c 			ctx->csa.class_1_dar = spu->class_1_dar;
csa                72 arch/powerpc/platforms/cell/spufs/run.c 	dsisr = ctx->csa.class_1_dsisr;
csa                76 arch/powerpc/platforms/cell/spufs/run.c 	if (ctx->csa.class_0_pending)
csa               240 arch/powerpc/platforms/cell/spufs/sched.c 	spu_restore(&ctx->csa, spu);
csa               445 arch/powerpc/platforms/cell/spufs/sched.c 	spu_save(&ctx->csa, spu);
csa                69 arch/powerpc/platforms/cell/spufs/spufs.h 	struct spu_state csa;		  /* SPU context save area. */
csa               348 arch/powerpc/platforms/cell/spufs/spufs.h extern int spu_init_csa(struct spu_state *csa);
csa               349 arch/powerpc/platforms/cell/spufs/spufs.h extern void spu_fini_csa(struct spu_state *csa);
csa               354 arch/powerpc/platforms/cell/spufs/spufs.h extern int spu_alloc_lscsa(struct spu_state *csa);
csa               355 arch/powerpc/platforms/cell/spufs/spufs.h extern void spu_free_lscsa(struct spu_state *csa);
csa                81 arch/powerpc/platforms/cell/spufs/switch.c static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
csa                97 arch/powerpc/platforms/cell/spufs/switch.c static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
csa               111 arch/powerpc/platforms/cell/spufs/switch.c 	if (csa) {
csa               112 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
csa               113 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
csa               114 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
csa               134 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
csa               147 arch/powerpc/platforms/cell/spufs/switch.c static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
csa               158 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
csa               167 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
csa               182 arch/powerpc/platforms/cell/spufs/switch.c 		if (csa)
csa               183 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.mfc_control_RW =
csa               192 arch/powerpc/platforms/cell/spufs/switch.c 		if (csa)
csa               193 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.mfc_control_RW =
csa               201 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
csa               209 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
csa               212 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
csa               217 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
csa               220 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
csa               228 arch/powerpc/platforms/cell/spufs/switch.c 		csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
csa               240 arch/powerpc/platforms/cell/spufs/switch.c 			csa->prob.spu_status_R = SPU_STATUS_RUNNING;
csa               242 arch/powerpc/platforms/cell/spufs/switch.c 			csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
csa               246 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_stopped_status(struct spu_state *csa,
csa               259 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.mfc_control_RW &= ~mask;
csa               260 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
csa               263 arch/powerpc/platforms/cell/spufs/switch.c static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
csa               276 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_timebase(struct spu_state *csa, struct spu *spu)
csa               282 arch/powerpc/platforms/cell/spufs/switch.c 	csa->suspend_time = get_cycles();
csa               285 arch/powerpc/platforms/cell/spufs/switch.c static inline void remove_other_spu_access(struct spu_state *csa,
csa               294 arch/powerpc/platforms/cell/spufs/switch.c static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
csa               307 arch/powerpc/platforms/cell/spufs/switch.c static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
csa               319 arch/powerpc/platforms/cell/spufs/switch.c static inline void handle_pending_interrupts(struct spu_state *csa,
csa               333 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
csa               344 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.puq[i].mfc_cq_data0_RW =
csa               346 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.puq[i].mfc_cq_data1_RW =
csa               348 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.puq[i].mfc_cq_data2_RW =
csa               350 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.puq[i].mfc_cq_data3_RW =
csa               354 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.spuq[i].mfc_cq_data0_RW =
csa               356 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.spuq[i].mfc_cq_data1_RW =
csa               358 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.spuq[i].mfc_cq_data2_RW =
csa               360 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv2.spuq[i].mfc_cq_data3_RW =
csa               366 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
csa               374 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
csa               377 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
csa               385 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
csa               388 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
csa               398 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
csa               401 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
csa               409 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_tag_status_query_RW =
csa               413 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
csa               421 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
csa               422 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
csa               425 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
csa               433 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
csa               436 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
csa               442 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
csa               445 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
csa               456 arch/powerpc/platforms/cell/spufs/switch.c static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
csa               470 arch/powerpc/platforms/cell/spufs/switch.c static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
csa               483 arch/powerpc/platforms/cell/spufs/switch.c static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
csa               501 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
csa               508 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
csa               511 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
csa               518 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
csa               521 arch/powerpc/platforms/cell/spufs/switch.c static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
csa               533 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
csa               540 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
csa               543 arch/powerpc/platforms/cell/spufs/switch.c static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
csa               555 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
csa               562 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
csa               565 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
csa               573 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
csa               579 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.resource_allocation_groupID_RW =
csa               581 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.resource_allocation_enable_RW =
csa               585 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
csa               592 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
csa               595 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
csa               602 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
csa               605 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
csa               612 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
csa               615 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
csa               626 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
csa               633 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
csa               634 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
csa               641 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
csa               651 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
csa               653 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
csa               659 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
csa               668 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
csa               672 arch/powerpc/platforms/cell/spufs/switch.c static inline void reset_ch(struct spu_state *csa, struct spu *spu)
csa               692 arch/powerpc/platforms/cell/spufs/switch.c static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
csa               703 arch/powerpc/platforms/cell/spufs/switch.c static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu,
csa               721 arch/powerpc/platforms/cell/spufs/switch.c 	spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size);
csa               724 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
csa               736 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
csa               741 arch/powerpc/platforms/cell/spufs/switch.c static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
csa               798 arch/powerpc/platforms/cell/spufs/switch.c static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
csa               800 arch/powerpc/platforms/cell/spufs/switch.c 	unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
csa               814 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
csa               831 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_signot1(struct spu_state *csa, struct spu *spu)
csa               844 arch/powerpc/platforms/cell/spufs/switch.c 	addr64.ull = (u64) csa->lscsa;
csa               849 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_signot2(struct spu_state *csa, struct spu *spu)
csa               862 arch/powerpc/platforms/cell/spufs/switch.c 	addr64.ull = (u64) csa->lscsa;
csa               867 arch/powerpc/platforms/cell/spufs/switch.c static inline void send_save_code(struct spu_state *csa, struct spu *spu)
csa               883 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
csa               896 arch/powerpc/platforms/cell/spufs/switch.c static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
csa               919 arch/powerpc/platforms/cell/spufs/switch.c static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
csa               938 arch/powerpc/platforms/cell/spufs/switch.c static inline int check_save_status(struct spu_state *csa, struct spu *spu)
csa               953 arch/powerpc/platforms/cell/spufs/switch.c static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
csa               961 arch/powerpc/platforms/cell/spufs/switch.c static inline void suspend_mfc_and_halt_decr(struct spu_state *csa,
csa               975 arch/powerpc/platforms/cell/spufs/switch.c static inline void wait_suspend_mfc_complete(struct spu_state *csa,
csa               989 arch/powerpc/platforms/cell/spufs/switch.c static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
csa              1031 arch/powerpc/platforms/cell/spufs/switch.c static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
csa              1065 arch/powerpc/platforms/cell/spufs/switch.c static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
csa              1090 arch/powerpc/platforms/cell/spufs/switch.c static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
csa              1110 arch/powerpc/platforms/cell/spufs/switch.c static inline void setup_spu_status_part1(struct spu_state *csa,
csa              1136 arch/powerpc/platforms/cell/spufs/switch.c 	    (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
csa              1137 arch/powerpc/platforms/cell/spufs/switch.c 	if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
csa              1143 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
csa              1144 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[1] = status_code;
csa              1146 arch/powerpc/platforms/cell/spufs/switch.c 	} else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
csa              1152 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
csa              1153 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[1] = status_code;
csa              1155 arch/powerpc/platforms/cell/spufs/switch.c 	} else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
csa              1160 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
csa              1161 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[1] = status_code;
csa              1163 arch/powerpc/platforms/cell/spufs/switch.c 	} else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
csa              1168 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
csa              1169 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[1] = status_code;
csa              1171 arch/powerpc/platforms/cell/spufs/switch.c 	} else if ((csa->prob.spu_status_R & status_P) == status_P) {
csa              1176 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
csa              1177 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[1] = status_code;
csa              1179 arch/powerpc/platforms/cell/spufs/switch.c 	} else if ((csa->prob.spu_status_R & status_H) == status_H) {
csa              1184 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
csa              1186 arch/powerpc/platforms/cell/spufs/switch.c 	} else if ((csa->prob.spu_status_R & status_S) == status_S) {
csa              1190 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
csa              1192 arch/powerpc/platforms/cell/spufs/switch.c 	} else if ((csa->prob.spu_status_R & status_I) == status_I) {
csa              1197 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
csa              1202 arch/powerpc/platforms/cell/spufs/switch.c static inline void setup_spu_status_part2(struct spu_state *csa,
csa              1221 arch/powerpc/platforms/cell/spufs/switch.c 	if (!(csa->prob.spu_status_R & mask)) {
csa              1222 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
csa              1226 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
csa              1233 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv1.resource_allocation_groupID_RW);
csa              1235 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv1.resource_allocation_enable_RW);
csa              1238 arch/powerpc/platforms/cell/spufs/switch.c static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
csa              1254 arch/powerpc/platforms/cell/spufs/switch.c static inline void setup_decr(struct spu_state *csa, struct spu *spu)
csa              1263 arch/powerpc/platforms/cell/spufs/switch.c 	if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
csa              1265 arch/powerpc/platforms/cell/spufs/switch.c 		cycles_t delta_time = resume_time - csa->suspend_time;
csa              1267 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING;
csa              1268 arch/powerpc/platforms/cell/spufs/switch.c 		if (csa->lscsa->decr.slot[0] < delta_time) {
csa              1269 arch/powerpc/platforms/cell/spufs/switch.c 			csa->lscsa->decr_status.slot[0] |=
csa              1273 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->decr.slot[0] -= delta_time;
csa              1275 arch/powerpc/platforms/cell/spufs/switch.c 		csa->lscsa->decr_status.slot[0] = 0;
csa              1279 arch/powerpc/platforms/cell/spufs/switch.c static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
csa              1284 arch/powerpc/platforms/cell/spufs/switch.c 	csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
csa              1287 arch/powerpc/platforms/cell/spufs/switch.c static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
csa              1292 arch/powerpc/platforms/cell/spufs/switch.c 	csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
csa              1295 arch/powerpc/platforms/cell/spufs/switch.c static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
csa              1310 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
csa              1317 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
csa              1321 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
csa              1333 arch/powerpc/platforms/cell/spufs/switch.c 	if (csa->prob.spu_status_R & mask) {
csa              1341 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
csa              1356 arch/powerpc/platforms/cell/spufs/switch.c 	if (!(csa->prob.spu_status_R & mask)) {
csa              1368 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
csa              1370 arch/powerpc/platforms/cell/spufs/switch.c 	unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
csa              1384 arch/powerpc/platforms/cell/spufs/switch.c static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
csa              1396 arch/powerpc/platforms/cell/spufs/switch.c static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
csa              1416 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
csa              1425 arch/powerpc/platforms/cell/spufs/switch.c 	if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
csa              1428 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.puq[i].mfc_cq_data0_RW);
csa              1430 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.puq[i].mfc_cq_data1_RW);
csa              1432 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.puq[i].mfc_cq_data2_RW);
csa              1434 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.puq[i].mfc_cq_data3_RW);
csa              1438 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.spuq[i].mfc_cq_data0_RW);
csa              1440 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.spuq[i].mfc_cq_data1_RW);
csa              1442 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.spuq[i].mfc_cq_data2_RW);
csa              1444 arch/powerpc/platforms/cell/spufs/switch.c 				 csa->priv2.spuq[i].mfc_cq_data3_RW);
csa              1450 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
csa              1457 arch/powerpc/platforms/cell/spufs/switch.c 	out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
csa              1461 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
csa              1468 arch/powerpc/platforms/cell/spufs/switch.c 	out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
csa              1472 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
csa              1480 arch/powerpc/platforms/cell/spufs/switch.c 		 csa->priv2.spu_tag_status_query_RW);
csa              1484 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
csa              1492 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
csa              1493 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
csa              1497 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
csa              1504 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
csa              1507 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
csa              1512 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
csa              1516 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
csa              1529 arch/powerpc/platforms/cell/spufs/switch.c 	ch0_cnt = csa->spu_chnlcnt_RW[0];
csa              1530 arch/powerpc/platforms/cell/spufs/switch.c 	ch0_data = csa->spu_chnldata_RW[0];
csa              1531 arch/powerpc/platforms/cell/spufs/switch.c 	ch1_data = csa->spu_chnldata_RW[1];
csa              1532 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
csa              1535 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_chnlcnt_RW[0] = 1;
csa              1539 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
csa              1546 arch/powerpc/platforms/cell/spufs/switch.c 	if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED))
csa              1549 arch/powerpc/platforms/cell/spufs/switch.c 	if ((csa->spu_chnlcnt_RW[0] == 0) &&
csa              1550 arch/powerpc/platforms/cell/spufs/switch.c 	    (csa->spu_chnldata_RW[1] & 0x20) &&
csa              1551 arch/powerpc/platforms/cell/spufs/switch.c 	    !(csa->spu_chnldata_RW[0] & 0x20))
csa              1552 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_chnlcnt_RW[0] = 1;
csa              1554 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnldata_RW[0] |= 0x20;
csa              1557 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
csa              1570 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
csa              1571 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
csa              1576 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
csa              1588 arch/powerpc/platforms/cell/spufs/switch.c 	ch_counts[1] = csa->spu_chnlcnt_RW[21];
csa              1599 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
csa              1606 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
csa              1610 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
csa              1617 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
csa              1621 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
csa              1629 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
csa              1636 arch/powerpc/platforms/cell/spufs/switch.c 	out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
csa              1640 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
csa              1650 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
csa              1652 arch/powerpc/platforms/cell/spufs/switch.c 		out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
csa              1657 arch/powerpc/platforms/cell/spufs/switch.c static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
csa              1666 arch/powerpc/platforms/cell/spufs/switch.c 	if ((csa->prob.mb_stat_R & 0xFF) == 0) {
csa              1672 arch/powerpc/platforms/cell/spufs/switch.c static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
csa              1681 arch/powerpc/platforms/cell/spufs/switch.c 	if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
csa              1689 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
csa              1694 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
csa              1698 arch/powerpc/platforms/cell/spufs/switch.c static inline void set_int_route(struct spu_state *csa, struct spu *spu)
csa              1705 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_other_spu_access(struct spu_state *csa,
csa              1713 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
csa              1721 arch/powerpc/platforms/cell/spufs/switch.c 	if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
csa              1727 arch/powerpc/platforms/cell/spufs/switch.c static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
csa              1734 arch/powerpc/platforms/cell/spufs/switch.c 	out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
csa              1747 arch/powerpc/platforms/cell/spufs/switch.c static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
csa              1757 arch/powerpc/platforms/cell/spufs/switch.c static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
csa              1765 arch/powerpc/platforms/cell/spufs/switch.c static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
csa              1771 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
csa              1772 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
csa              1773 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
csa              2135 arch/powerpc/platforms/cell/spufs/switch.c static void init_prob(struct spu_state *csa)
csa              2137 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[9] = 1;
csa              2138 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[21] = 16;
csa              2139 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[23] = 1;
csa              2140 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[28] = 1;
csa              2141 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[30] = 1;
csa              2142 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
csa              2143 arch/powerpc/platforms/cell/spufs/switch.c 	csa->prob.mb_stat_R = 0x000400;
csa              2146 arch/powerpc/platforms/cell/spufs/switch.c static void init_priv1(struct spu_state *csa)
csa              2149 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
csa              2155 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
csa              2158 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
csa              2160 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
csa              2165 arch/powerpc/platforms/cell/spufs/switch.c static void init_priv2(struct spu_state *csa)
csa              2167 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
csa              2168 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
csa              2184 arch/powerpc/platforms/cell/spufs/switch.c int spu_init_csa(struct spu_state *csa)
csa              2188 arch/powerpc/platforms/cell/spufs/switch.c 	if (!csa)
csa              2190 arch/powerpc/platforms/cell/spufs/switch.c 	memset(csa, 0, sizeof(struct spu_state));
csa              2192 arch/powerpc/platforms/cell/spufs/switch.c 	rc = spu_alloc_lscsa(csa);
csa              2196 arch/powerpc/platforms/cell/spufs/switch.c 	spin_lock_init(&csa->register_lock);
csa              2198 arch/powerpc/platforms/cell/spufs/switch.c 	init_prob(csa);
csa              2199 arch/powerpc/platforms/cell/spufs/switch.c 	init_priv1(csa);
csa              2200 arch/powerpc/platforms/cell/spufs/switch.c 	init_priv2(csa);
csa              2205 arch/powerpc/platforms/cell/spufs/switch.c void spu_fini_csa(struct spu_state *csa)
csa              2207 arch/powerpc/platforms/cell/spufs/switch.c 	spu_free_lscsa(csa);
csa               654 drivers/net/wireless/intel/ipw2x00/libipw.h 	struct libipw_csa csa;
csa              4110 drivers/net/wireless/intel/iwlegacy/common.c 	struct il_csa_notification *csa = &(pkt->u.csa_notif);
csa              4116 drivers/net/wireless/intel/iwlegacy/common.c 	if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
csa              4117 drivers/net/wireless/intel/iwlegacy/common.c 		rxon->channel = csa->channel;
csa              4118 drivers/net/wireless/intel/iwlegacy/common.c 		il->staging.channel = csa->channel;
csa              4119 drivers/net/wireless/intel/iwlegacy/common.c 		D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
csa              4123 drivers/net/wireless/intel/iwlegacy/common.c 		       le16_to_cpu(csa->channel));
csa                52 drivers/net/wireless/intel/iwlwifi/dvm/rx.c 	struct iwl_csa_notification *csa = (void *)pkt->data;
csa                63 drivers/net/wireless/intel/iwlwifi/dvm/rx.c 	if (!le32_to_cpu(csa->status) && csa->channel == priv->switch_channel) {
csa                64 drivers/net/wireless/intel/iwlwifi/dvm/rx.c 		rxon->channel = csa->channel;
csa                65 drivers/net/wireless/intel/iwlwifi/dvm/rx.c 		ctx->staging.channel = csa->channel;
csa                67 drivers/net/wireless/intel/iwlwifi/dvm/rx.c 			      le16_to_cpu(csa->channel));
csa                71 drivers/net/wireless/intel/iwlwifi/dvm/rx.c 			le16_to_cpu(csa->channel));
csa               737 kernel/cgroup/cpuset.c 	struct cpuset **csa;	/* array of all cpuset ptrs */
csa               749 kernel/cgroup/cpuset.c 	csa = NULL;
csa               769 kernel/cgroup/cpuset.c 	csa = kmalloc_array(nr_cpusets(), sizeof(cp), GFP_KERNEL);
csa               770 kernel/cgroup/cpuset.c 	if (!csa)
csa               776 kernel/cgroup/cpuset.c 		csa[csn++] = &top_cpuset;
csa               803 kernel/cgroup/cpuset.c 			csa[csn++] = cp;
csa               812 kernel/cgroup/cpuset.c 		csa[i]->pn = i;
csa               818 kernel/cgroup/cpuset.c 		struct cpuset *a = csa[i];
csa               822 kernel/cgroup/cpuset.c 			struct cpuset *b = csa[j];
csa               827 kernel/cgroup/cpuset.c 					struct cpuset *c = csa[k];
csa               854 kernel/cgroup/cpuset.c 		struct cpuset *a = csa[i];
csa               879 kernel/cgroup/cpuset.c 			struct cpuset *b = csa[j];
csa               896 kernel/cgroup/cpuset.c 	kfree(csa);
csa               801 net/mac80211/cfg.c 				    const struct ieee80211_csa_settings *csa)
csa               817 net/mac80211/cfg.c 	if (csa)
csa               818 net/mac80211/cfg.c 		memcpy(new->csa_counter_offsets, csa->counter_offsets_presp,
csa               819 net/mac80211/cfg.c 		       csa->n_counter_offsets_presp *
csa               873 net/mac80211/cfg.c 				   const struct ieee80211_csa_settings *csa)
csa               917 net/mac80211/cfg.c 	if (csa) {
csa               918 net/mac80211/cfg.c 		new->csa_current_counter = csa->count;
csa               919 net/mac80211/cfg.c 		memcpy(new->csa_counter_offsets, csa->counter_offsets_beacon,
csa               920 net/mac80211/cfg.c 		       csa->n_counter_offsets_beacon *
csa               938 net/mac80211/cfg.c 				       params->probe_resp_len, csa);
csa              3192 net/mac80211/cfg.c 	struct ieee80211_csa_settings csa = {};
csa              3227 net/mac80211/cfg.c 		csa.counter_offsets_beacon = params->counter_offsets_beacon;
csa              3228 net/mac80211/cfg.c 		csa.counter_offsets_presp = params->counter_offsets_presp;
csa              3229 net/mac80211/cfg.c 		csa.n_counter_offsets_beacon = params->n_counter_offsets_beacon;
csa              3230 net/mac80211/cfg.c 		csa.n_counter_offsets_presp = params->n_counter_offsets_presp;
csa              3231 net/mac80211/cfg.c 		csa.count = params->count;
csa              3233 net/mac80211/cfg.c 		err = ieee80211_assign_beacon(sdata, &params->beacon_csa, &csa);
csa               708 net/mac80211/ieee80211_i.h 	struct mesh_csa_settings __rcu *csa;
csa               733 net/mac80211/mesh.c 	struct mesh_csa_settings *csa;
csa               802 net/mac80211/mesh.c 	csa = rcu_dereference(ifmsh->csa);
csa               803 net/mac80211/mesh.c 	if (csa) {
csa               814 net/mac80211/mesh.c 				csa->settings.chandef.chan->center_freq);
csa               815 net/mac80211/mesh.c 		bcn->csa_current_counter = csa->settings.count;
csa               817 net/mac80211/mesh.c 		*pos++ = csa->settings.count;
csa               826 net/mac80211/mesh.c 		*pos++ |= csa->settings.block_tx ?
csa               833 net/mac80211/mesh.c 		switch (csa->settings.chandef.width) {
csa               840 net/mac80211/mesh.c 			ct = cfg80211_get_chandef_type(&csa->settings.chandef);
csa               857 net/mac80211/mesh.c 			chandef = &csa->settings.chandef;
csa              1283 net/mac80211/mesh.c 	tmp_csa_settings = rcu_dereference_protected(ifmsh->csa,
csa              1285 net/mac80211/mesh.c 	RCU_INIT_POINTER(ifmsh->csa, NULL);
csa              1316 net/mac80211/mesh.c 	rcu_assign_pointer(ifmsh->csa, tmp_csa_settings);
csa              1320 net/mac80211/mesh.c 		tmp_csa_settings = rcu_dereference(ifmsh->csa);
csa              1321 net/mac80211/mesh.c 		RCU_INIT_POINTER(ifmsh->csa, NULL);