cs_mask 33 arch/arm/include/asm/vdso_datapage.h u64 cs_mask; /* clocksource mask */ cs_mask 334 arch/arm/kernel/vdso.c vdso_data->cs_mask = tk->tkr_mono.mask; cs_mask 117 arch/arm/vdso/vgettimeofday.c cycle_delta = (cycle_now - vdata->cs_cycle_last) & vdata->cs_mask; cs_mask 1625 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 1627 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 1639 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 1641 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 1986 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 1988 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 2003 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 2005 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t cs_mask:8; cs_mask 26 arch/nds32/include/asm/vdso_datapage.h u64 cs_mask; /* clocksource mask */ cs_mask 212 arch/nds32/kernel/vdso.c vdso_data->cs_mask = tk->tkr_mono.mask; cs_mask 115 arch/nds32/kernel/vdso/gettimeofday.c return ((u64) cycle_delta & vdso->cs_mask) * vdso->cs_mult; cs_mask 675 arch/x86/kernel/cpu/mce/amd.c u8 cs_mask, cs_id = 0; cs_mask 781 arch/x86/kernel/cpu/mce/amd.c cs_mask = (1 << die_id_bit) - 1; cs_mask 782 arch/x86/kernel/cpu/mce/amd.c cs_id = cs_fabric_id & cs_mask; cs_mask 1829 drivers/edac/amd64_edac.c u64 cs_base, cs_mask; cs_mask 1845 drivers/edac/amd64_edac.c get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); cs_mask 1848 drivers/edac/amd64_edac.c csrow, cs_base, cs_mask); cs_mask 1850 drivers/edac/amd64_edac.c cs_mask = ~cs_mask; cs_mask 1853 drivers/edac/amd64_edac.c (in_addr & cs_mask), (cs_base & cs_mask)); cs_mask 1855 drivers/edac/amd64_edac.c if ((in_addr & cs_mask) == (cs_base & cs_mask)) { cs_mask 52 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->cs_shift->field_name, clk_src->cs_mask->field_name cs_mask 831 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) cs_mask 1317 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c const struct dce110_clk_src_mask *cs_mask) cs_mask 1329 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->cs_mask = cs_mask; cs_mask 1342 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->cs_mask->PLL_POST_DIV_PIXCLK; cs_mask 1344 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; cs_mask 1361 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->cs_mask->PLL_POST_DIV_PIXCLK; cs_mask 1363 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; cs_mask 1417 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c const struct dce110_clk_src_mask *cs_mask) cs_mask 1426 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c clk_src->cs_mask = cs_mask; cs_mask 1446 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c const struct dce110_clk_src_mask *cs_mask) cs_mask 1448 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); cs_mask 166 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h const struct dce110_clk_src_mask *cs_mask; cs_mask 193 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h const struct dce110_clk_src_mask *cs_mask); cs_mask 202 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h const struct dce110_clk_src_mask *cs_mask); cs_mask 212 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h const struct dce110_clk_src_mask *cs_mask); cs_mask 326 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 666 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 356 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 712 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 362 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 685 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 377 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 498 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 345 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 699 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 784 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 1186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 345 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dce110_clk_src_mask cs_mask = { cs_mask 1136 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c regs, &cs_shift, &cs_mask)) { cs_mask 706 drivers/pcmcia/i82365.c u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); cs_mask 708 drivers/pcmcia/i82365.c if ((cs_mask & (1 << cs_irq)) && cs_mask 463 drivers/pcmcia/tcic.c u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); cs_mask 465 drivers/pcmcia/tcic.c if ((cs_mask & (1 << i)) && cs_mask 131 drivers/spi/spi-dln2.c static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask) cs_mask 145 drivers/spi/spi-dln2.c tx.cs = ~cs_mask; cs_mask 161 drivers/spi/spi-dln2.c static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable) cs_mask 170 drivers/spi/spi-dln2.c tx.cs = cs_mask; cs_mask 178 drivers/spi/spi-dln2.c u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0); cs_mask 180 drivers/spi/spi-dln2.c return dln2_spi_cs_enable(dln2, cs_mask, enable); cs_mask 583 drivers/usb/host/ehci-dbg.c ps->bw_period, ps->cs_mask); cs_mask 203 drivers/usb/host/ehci-sched.c ps->usecs, ps->c_usecs, ps->cs_mask); cs_mask 239 drivers/usb/host/ehci-sched.c if (qh->ps.cs_mask & m) cs_mask 904 drivers/usb/host/ehci-sched.c qh->ps.cs_mask = qh->ps.period ? cs_mask 910 drivers/usb/host/ehci-sched.c hw->hw_info2 |= cpu_to_hc32(ehci, qh->ps.cs_mask); cs_mask 1106 drivers/usb/host/ehci-sched.c stream->ps.cs_mask = 1; cs_mask 1110 drivers/usb/host/ehci-sched.c stream->ps.cs_mask |= tmp << (8 + 2); cs_mask 1112 drivers/usb/host/ehci-sched.c stream->ps.cs_mask = smask_out[hs_transfers - 1]; cs_mask 1345 drivers/usb/host/ehci-sched.c s_mask = stream->ps.cs_mask; cs_mask 1404 drivers/usb/host/ehci-sched.c mask = stream->ps.cs_mask << (uframe & 7); cs_mask 1407 drivers/usb/host/ehci-sched.c if (((stream->ps.cs_mask & 0xff) << (uframe & 7)) >= (1 << 7)) cs_mask 1441 drivers/usb/host/ehci-sched.c for (tmp = stream->ps.cs_mask & 0xff; tmp; tmp >>= 1, uf++) { cs_mask 1453 drivers/usb/host/ehci-sched.c if ((stream->ps.cs_mask & tmp) == 0) cs_mask 1463 drivers/usb/host/ehci-sched.c stream->ps.cs_mask <<= uframe & 7; cs_mask 1464 drivers/usb/host/ehci-sched.c stream->splits = cpu_to_hc32(ehci, stream->ps.cs_mask); cs_mask 53 drivers/usb/host/ehci.h u16 cs_mask; /* C-mask and S-mask bytes */ cs_mask 56 sound/pci/ice1712/ak4xxx.c if (priv->cs_mask == priv->cs_addr) { cs_mask 58 sound/pci/ice1712/ak4xxx.c tmp |= priv->cs_mask; /* start without chip select */ cs_mask 60 sound/pci/ice1712/ak4xxx.c tmp &= ~priv->cs_mask; /* chip select low */ cs_mask 66 sound/pci/ice1712/ak4xxx.c tmp &= ~priv->cs_mask; cs_mask 93 sound/pci/ice1712/ak4xxx.c if (priv->cs_mask == priv->cs_addr) { cs_mask 96 sound/pci/ice1712/ak4xxx.c tmp &= ~priv->cs_mask; cs_mask 100 sound/pci/ice1712/ak4xxx.c tmp |= priv->cs_mask; /* chip select high to trigger */ cs_mask 102 sound/pci/ice1712/ak4xxx.c tmp &= ~priv->cs_mask; cs_mask 253 sound/pci/ice1712/delta.c priv->cs_mask = cs_mask 267 sound/pci/ice1712/delta.c priv->cs_mask = ICE1712_DELTA_1010LT_CS; cs_mask 280 sound/pci/ice1712/delta.c priv->cs_mask = cs_mask 294 sound/pci/ice1712/delta.c priv->cs_mask = cs_mask 448 sound/pci/ice1712/delta.c .cs_mask = ICE1712_DELTA_AP_CS_CODEC, cs_mask 469 sound/pci/ice1712/delta.c .cs_mask = ICE1712_DELTA_AP_CS_CODEC, cs_mask 491 sound/pci/ice1712/delta.c .cs_mask = 0, cs_mask 513 sound/pci/ice1712/delta.c .cs_mask = 0, cs_mask 536 sound/pci/ice1712/delta.c .cs_mask = 0, cs_mask 558 sound/pci/ice1712/delta.c .cs_mask = 0, cs_mask 205 sound/pci/ice1712/ews.c tmp = priv->cs_mask = priv->cs_addr = (1 << chip) & ICE1712_6FIRE_AK4524_CS_MASK; cs_mask 348 sound/pci/ice1712/ews.c .cs_mask = 0, cs_mask 369 sound/pci/ice1712/ews.c .cs_mask = ICE1712_EWX2496_AK4524_CS, cs_mask 390 sound/pci/ice1712/ews.c .cs_mask = 0, cs_mask 292 sound/pci/ice1712/hoontech.c .cs_mask = ICE1712_STDSP24_AK4524_CS, cs_mask 256 sound/pci/ice1712/ice1712.h unsigned int cs_mask; /* bit mask for select/deselect address */ cs_mask 102 sound/pci/ice1712/phase.c .cs_mask = 1 << 10, cs_mask 238 sound/pci/ice1712/revo.c .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2, cs_mask 260 sound/pci/ice1712/revo.c .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2, cs_mask 281 sound/pci/ice1712/revo.c .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1, cs_mask 299 sound/pci/ice1712/revo.c .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1, cs_mask 349 sound/pci/ice1712/revo.c .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS3,