DC_MEM_GLOBAL_PWR_REQ_CNTL 131 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL)) DC_MEM_GLOBAL_PWR_REQ_CNTL 132 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_CNTL 49 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) DC_MEM_GLOBAL_PWR_REQ_CNTL 86 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ DC_MEM_GLOBAL_PWR_REQ_CNTL 158 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) DC_MEM_GLOBAL_PWR_REQ_CNTL 342 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; DC_MEM_GLOBAL_PWR_REQ_CNTL 451 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) DC_MEM_GLOBAL_PWR_REQ_CNTL 527 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) DC_MEM_GLOBAL_PWR_REQ_CNTL 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);