DC_IP_REQUEST_CNTL  210 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DC_IP_REQUEST_CNTL), \
DC_IP_REQUEST_CNTL  277 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DC_IP_REQUEST_CNTL), \
DC_IP_REQUEST_CNTL  330 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(DC_IP_REQUEST_CNTL), \
DC_IP_REQUEST_CNTL  363 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t DC_IP_REQUEST_CNTL;
DC_IP_REQUEST_CNTL  571 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
DC_IP_REQUEST_CNTL  638 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
DC_IP_REQUEST_CNTL  681 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
DC_IP_REQUEST_CNTL  605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (REG(DC_IP_REQUEST_CNTL)) {
DC_IP_REQUEST_CNTL  606 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL  610 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL  627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL  631 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL  656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL  660 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL 1013 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (REG(DC_IP_REQUEST_CNTL)) {
DC_IP_REQUEST_CNTL 1014 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL 1019 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL  262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
DC_IP_REQUEST_CNTL  264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
DC_IP_REQUEST_CNTL  321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
DC_IP_REQUEST_CNTL  913 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (REG(DC_IP_REQUEST_CNTL)) {
DC_IP_REQUEST_CNTL  914 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_SET(DC_IP_REQUEST_CNTL, 0,
DC_IP_REQUEST_CNTL  918 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		REG_SET(DC_IP_REQUEST_CNTL, 0,