crtcstate          52 drivers/gpu/drm/nouveau/dispnv04/crtc.c crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
crtcstate          55 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		       crtcstate->CRTC[index]);
crtcstate          31 drivers/gpu/drm/nouveau/dispnv04/cursor.c crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
crtcstate          34 drivers/gpu/drm/nouveau/dispnv04/cursor.c 		       crtcstate->CRTC[index]);
crtcstate          95 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
crtcstate         108 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
crtcstate         109 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
crtcstate         250 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
crtcstate         251 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
crtcstate         252 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
crtcstate         378 drivers/gpu/drm/nouveau/dispnv04/hw.c 	     struct nv04_crtc_reg *crtcstate, int index)
crtcstate         380 drivers/gpu/drm/nouveau/dispnv04/hw.c 	crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
crtcstate         385 drivers/gpu/drm/nouveau/dispnv04/hw.c 	     struct nv04_crtc_reg *crtcstate, int index)
crtcstate         387 drivers/gpu/drm/nouveau/dispnv04/hw.c 	NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);