DC_I2C_CONTROL     54 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE_5(DC_I2C_CONTROL,
DC_I2C_CONTROL     62 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
DC_I2C_CONTROL    272 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE_2(DC_I2C_CONTROL,
DC_I2C_CONTROL    311 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 	REG_UPDATE_6(DC_I2C_CONTROL,
DC_I2C_CONTROL    365 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		REG_UPDATE_2(DC_I2C_CONTROL,
DC_I2C_CONTROL    369 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c 		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
DC_I2C_CONTROL     89 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	SR(DC_I2C_CONTROL),\
DC_I2C_CONTROL    114 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
DC_I2C_CONTROL    115 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
DC_I2C_CONTROL    116 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
DC_I2C_CONTROL    117 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
DC_I2C_CONTROL    118 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
DC_I2C_CONTROL    119 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
DC_I2C_CONTROL    240 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h 	uint32_t DC_I2C_CONTROL;