crtc_reg           62 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg           77 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg          120 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
crtc_reg          236 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg          461 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg          462 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
crtc_reg          541 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
crtc_reg          664 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
crtc_reg          666 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
crtc_reg          685 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
crtc_reg          770 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
crtc_reg          824 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg           42 drivers/gpu/drm/nouveau/dispnv04/cursor.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg           95 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
crtc_reg          122 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
crtc_reg          137 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
crtc_reg          250 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
crtc_reg          287 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg          288 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
crtc_reg          463 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
crtc_reg          603 drivers/gpu/drm/nouveau/dispnv04/dfp.c 					(&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
crtc_reg           74 drivers/gpu/drm/nouveau/dispnv04/disp.h 	struct nv04_crtc_reg crtc_reg[2];
crtc_reg          395 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
crtc_reg          471 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
crtc_reg          541 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
crtc_reg          565 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
crtc_reg          592 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
crtc_reg          668 drivers/gpu/drm/nouveau/dispnv04/hw.c 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];
crtc_reg          785 drivers/gpu/drm/nouveau/dispnv04/hw.c 		state->crtc_reg[head].DAC[i] = nvif_rd08(device,
crtc_reg          805 drivers/gpu/drm/nouveau/dispnv04/hw.c 				state->crtc_reg[head].DAC[i]);
crtc_reg          376 drivers/gpu/drm/nouveau/dispnv04/hw.h 		&nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
crtc_reg          547 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
crtc_reg          107 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 	struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
crtc_reg          146 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
crtc_reg          403 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
crtc_reg          464 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];