crtc_offsets 53 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static const u32 crtc_offsets[] = crtc_offsets 204 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); crtc_offsets 266 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); crtc_offsets 267 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 414 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); crtc_offsets 416 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 424 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 485 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), crtc_offsets 488 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 489 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); crtc_offsets 491 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 492 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 2965 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 2968 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 2971 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 2974 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 2994 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 2997 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 3000 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 3003 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 3100 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); crtc_offsets 3102 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 3105 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 3128 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & crtc_offsets 3130 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], crtc_offsets 3189 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); crtc_offsets 3191 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); crtc_offsets 3204 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); crtc_offsets 3206 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); crtc_offsets 53 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static const u32 crtc_offsets[] = crtc_offsets 222 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); crtc_offsets 284 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); crtc_offsets 285 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 430 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); crtc_offsets 432 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 440 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 511 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), crtc_offsets 514 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 515 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); crtc_offsets 517 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 518 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 3091 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 3094 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 3097 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 3100 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 3120 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 3123 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 3126 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); crtc_offsets 3129 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); crtc_offsets 3226 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); crtc_offsets 3228 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 3231 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 3254 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & crtc_offsets 3256 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], crtc_offsets 3315 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); crtc_offsets 3317 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); crtc_offsets 3330 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); crtc_offsets 3332 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); crtc_offsets 57 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static const u32 crtc_offsets[6] = crtc_offsets 156 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); crtc_offsets 217 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); crtc_offsets 218 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 382 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & crtc_offsets 385 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 386 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); crtc_offsets 388 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 389 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 2580 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; crtc_offsets 2940 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); crtc_offsets 2951 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); crtc_offsets 2977 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); crtc_offsets 2979 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 2982 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 3005 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & crtc_offsets 3007 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], crtc_offsets 54 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static const u32 crtc_offsets[6] = crtc_offsets 152 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); crtc_offsets 211 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); crtc_offsets 212 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 348 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { crtc_offsets 349 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 357 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 425 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), crtc_offsets 428 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 429 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); crtc_offsets 431 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 432 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 2600 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; crtc_offsets 3032 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); crtc_offsets 3043 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); crtc_offsets 3069 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); crtc_offsets 3071 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 3074 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], crtc_offsets 3097 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & crtc_offsets 3099 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], crtc_offsets 65 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c static const u32 crtc_offsets[6] = crtc_offsets 115 drivers/gpu/drm/radeon/evergreen.c static const u32 crtc_offsets[6] = crtc_offsets 1353 drivers/gpu/drm/radeon/evergreen.c if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) crtc_offsets 1363 drivers/gpu/drm/radeon/evergreen.c pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 1364 drivers/gpu/drm/radeon/evergreen.c pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 1387 drivers/gpu/drm/radeon/evergreen.c if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) crtc_offsets 2679 drivers/gpu/drm/radeon/evergreen.c crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; crtc_offsets 2683 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); crtc_offsets 2686 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 2688 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); crtc_offsets 2689 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 2692 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); crtc_offsets 2695 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 2697 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 2698 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 2720 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 2721 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); crtc_offsets 2723 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 2724 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 2748 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); crtc_offsets 2751 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); crtc_offsets 2753 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); crtc_offsets 2756 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); crtc_offsets 2769 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], crtc_offsets 2771 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], crtc_offsets 2773 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], crtc_offsets 2775 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], crtc_offsets 2787 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); crtc_offsets 2790 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); crtc_offsets 2792 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); crtc_offsets 2795 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); crtc_offsets 2797 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); crtc_offsets 2800 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); crtc_offsets 2803 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); crtc_offsets 2821 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); crtc_offsets 2823 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 2824 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); crtc_offsets 2825 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 2827 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); crtc_offsets 2829 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 2830 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 2831 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 3804 drivers/gpu/drm/radeon/evergreen.c if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) { crtc_offsets 3805 drivers/gpu/drm/radeon/evergreen.c crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 3813 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 4455 drivers/gpu/drm/radeon/evergreen.c return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); crtc_offsets 4477 drivers/gpu/drm/radeon/evergreen.c WREG32(INT_MASK + crtc_offsets[i], 0); crtc_offsets 4479 drivers/gpu/drm/radeon/evergreen.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); crtc_offsets 4577 drivers/gpu/drm/radeon/evergreen.c rdev, INT_MASK + crtc_offsets[i], crtc_offsets 4584 drivers/gpu/drm/radeon/evergreen.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); crtc_offsets 4600 drivers/gpu/drm/radeon/evergreen.c rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], crtc_offsets 4621 drivers/gpu/drm/radeon/evergreen.c afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]); crtc_offsets 4623 drivers/gpu/drm/radeon/evergreen.c grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); crtc_offsets 4630 drivers/gpu/drm/radeon/evergreen.c WREG32(GRPH_INT_STATUS + crtc_offsets[j], crtc_offsets 4636 drivers/gpu/drm/radeon/evergreen.c WREG32(VBLANK_STATUS + crtc_offsets[j], crtc_offsets 4639 drivers/gpu/drm/radeon/evergreen.c WREG32(VLINE_STATUS + crtc_offsets[j], crtc_offsets 4656 drivers/gpu/drm/radeon/evergreen.c WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], crtc_offsets 100 drivers/gpu/drm/radeon/r600.c static const u32 crtc_offsets[2] = crtc_offsets 1594 drivers/gpu/drm/radeon/r600.c if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { crtc_offsets 1595 drivers/gpu/drm/radeon/r600.c crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 1603 drivers/gpu/drm/radeon/r600.c tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); crtc_offsets 55 drivers/gpu/drm/radeon/rs600.c static const u32 crtc_offsets[2] = crtc_offsets 63 drivers/gpu/drm/radeon/rs600.c if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) crtc_offsets 73 drivers/gpu/drm/radeon/rs600.c pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 74 drivers/gpu/drm/radeon/rs600.c pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); crtc_offsets 97 drivers/gpu/drm/radeon/rs600.c if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) crtc_offsets 48 drivers/gpu/drm/radeon/rv515.c static const u32 crtc_offsets[2] = crtc_offsets 310 drivers/gpu/drm/radeon/rv515.c crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; crtc_offsets 313 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); crtc_offsets 316 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 318 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 319 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 330 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); crtc_offsets 331 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); crtc_offsets 333 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 334 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); crtc_offsets 366 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); crtc_offsets 369 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); crtc_offsets 371 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); crtc_offsets 374 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); crtc_offsets 400 drivers/gpu/drm/radeon/rv515.c WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], crtc_offsets 402 drivers/gpu/drm/radeon/rv515.c WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], crtc_offsets 410 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); crtc_offsets 414 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); crtc_offsets 416 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); crtc_offsets 419 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); crtc_offsets 421 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); crtc_offsets 424 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); crtc_offsets 427 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); crtc_offsets 452 drivers/gpu/drm/radeon/rv515.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); crtc_offsets 454 drivers/gpu/drm/radeon/rv515.c WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); crtc_offsets 146 drivers/gpu/drm/radeon/si.c static const u32 crtc_offsets[] = crtc_offsets 5965 drivers/gpu/drm/radeon/si.c WREG32(INT_MASK + crtc_offsets[i], 0); crtc_offsets 5967 drivers/gpu/drm/radeon/si.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); crtc_offsets 6119 drivers/gpu/drm/radeon/si.c rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK, crtc_offsets 6125 drivers/gpu/drm/radeon/si.c WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); crtc_offsets 6157 drivers/gpu/drm/radeon/si.c grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); crtc_offsets 6164 drivers/gpu/drm/radeon/si.c WREG32(GRPH_INT_STATUS + crtc_offsets[j], crtc_offsets 6170 drivers/gpu/drm/radeon/si.c WREG32(VBLANK_STATUS + crtc_offsets[j], crtc_offsets 6173 drivers/gpu/drm/radeon/si.c WREG32(VLINE_STATUS + crtc_offsets[j],