crtc_offset_cntl  107 drivers/gpu/drm/r128/r128_drv.h 	u32 crtc_offset_cntl;
crtc_offset_cntl 1237 drivers/gpu/drm/r128/r128_state.c 	dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
crtc_offset_cntl 1241 drivers/gpu/drm/r128/r128_state.c 		   dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
crtc_offset_cntl 1256 drivers/gpu/drm/r128/r128_state.c 	R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
crtc_offset_cntl  384 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
crtc_offset_cntl  475 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	crtc_offset_cntl = 0;
crtc_offset_cntl  482 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
crtc_offset_cntl  485 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
crtc_offset_cntl  489 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
crtc_offset_cntl  492 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
crtc_offset_cntl  496 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
crtc_offset_cntl  507 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			crtc_offset_cntl |= (y % 16);
crtc_offset_cntl  554 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
crtc_offset_cntl  192 drivers/video/fbdev/aty/radeonfb.h 	u32		crtc_offset_cntl;