crtc_offset 385 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h uint32_t crtc_offset; crtc_offset 243 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 246 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 248 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, crtc_offset 251 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 254 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 257 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); crtc_offset 571 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 622 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); crtc_offset 624 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1119 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1121 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1122 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1125 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1128 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1129 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1132 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1134 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); crtc_offset 1824 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); crtc_offset 1826 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2003 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2006 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2008 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2010 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2012 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2014 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2016 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); crtc_offset 2017 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); crtc_offset 2024 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); crtc_offset 2029 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2034 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); crtc_offset 2035 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); crtc_offset 2036 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 2037 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 2038 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); crtc_offset 2039 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); crtc_offset 2042 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); crtc_offset 2046 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, crtc_offset 2051 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, crtc_offset 2055 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 2059 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2084 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); crtc_offset 2089 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2103 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2106 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2108 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2110 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2112 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2114 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2116 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2119 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2121 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 2123 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2124 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); crtc_offset 2125 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); crtc_offset 2127 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2128 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2129 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2131 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2132 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); crtc_offset 2134 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); crtc_offset 2139 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, crtc_offset 2145 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2149 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2151 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2154 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2156 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2159 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2161 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2164 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2167 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 2171 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2173 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2274 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); crtc_offset 2279 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); crtc_offset 2288 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2290 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2299 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2301 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2304 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2307 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2334 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); crtc_offset 2335 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); crtc_offset 2336 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 2695 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; crtc_offset 2698 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; crtc_offset 2701 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; crtc_offset 2704 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; crtc_offset 2707 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; crtc_offset 2710 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; crtc_offset 261 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 264 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 266 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, crtc_offset 269 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 272 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 275 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); crtc_offset 597 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 648 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); crtc_offset 650 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1145 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1147 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1148 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1151 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1154 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1155 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1158 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1160 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); crtc_offset 1866 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); crtc_offset 1868 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2045 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2048 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2050 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2052 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2054 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2056 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2058 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); crtc_offset 2059 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); crtc_offset 2066 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); crtc_offset 2071 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2076 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); crtc_offset 2077 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); crtc_offset 2078 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 2079 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 2080 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); crtc_offset 2081 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); crtc_offset 2084 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); crtc_offset 2088 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, crtc_offset 2093 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, crtc_offset 2097 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 2101 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2126 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); crtc_offset 2131 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2145 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2147 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2149 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2151 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2153 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2155 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2157 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 2159 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2160 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); crtc_offset 2161 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); crtc_offset 2163 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2164 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2165 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2167 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2168 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); crtc_offset 2170 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); crtc_offset 2175 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, crtc_offset 2181 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2185 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2187 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2189 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2191 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2193 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2195 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2197 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2200 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 2204 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2206 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2353 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); crtc_offset 2358 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); crtc_offset 2367 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2369 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2378 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2380 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2383 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 2386 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 2413 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); crtc_offset 2414 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); crtc_offset 2415 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 2803 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; crtc_offset 2806 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; crtc_offset 2809 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; crtc_offset 2812 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; crtc_offset 2815 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; crtc_offset 2818 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; crtc_offset 197 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? crtc_offset 200 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, crtc_offset 203 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 205 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 209 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); crtc_offset 449 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 952 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); crtc_offset 956 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); crtc_offset 957 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 961 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); crtc_offset 964 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); crtc_offset 965 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 969 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); crtc_offset 972 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); crtc_offset 973 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); crtc_offset 1017 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, crtc_offset 1784 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); crtc_offset 1944 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 1946 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 1948 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 1950 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 1952 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 1954 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); crtc_offset 1955 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); crtc_offset 1962 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, crtc_offset 1969 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); crtc_offset 1970 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); crtc_offset 1971 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 1972 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 1973 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); crtc_offset 1974 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); crtc_offset 1977 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); crtc_offset 1981 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, crtc_offset 1985 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, crtc_offset 1990 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 1994 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2020 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, crtc_offset 2023 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); crtc_offset 2037 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2040 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2042 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2044 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2048 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 2050 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2051 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); crtc_offset 2052 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); crtc_offset 2054 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2055 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2056 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2058 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2059 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); crtc_offset 2061 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); crtc_offset 2066 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, crtc_offset 2072 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2077 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2080 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2083 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2087 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); crtc_offset 2164 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); crtc_offset 2169 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); crtc_offset 2177 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2189 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2191 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2194 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2227 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); crtc_offset 2228 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); crtc_offset 2229 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 2580 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; crtc_offset 190 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? crtc_offset 193 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, crtc_offset 196 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 199 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 202 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); crtc_offset 508 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 559 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, crtc_offset 1054 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1058 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1059 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 1063 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); crtc_offset 1066 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); crtc_offset 1067 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 1071 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); crtc_offset 1753 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); crtc_offset 1755 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); crtc_offset 1918 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 1920 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 1922 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 1924 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 1926 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 1928 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); crtc_offset 1929 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); crtc_offset 1936 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 1943 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); crtc_offset 1944 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); crtc_offset 1945 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 1946 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); crtc_offset 1947 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); crtc_offset 1948 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); crtc_offset 1951 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); crtc_offset 1955 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, crtc_offset 1960 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, crtc_offset 1964 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 1968 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 1993 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, crtc_offset 1996 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); crtc_offset 2009 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2012 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2014 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2016 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2020 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); crtc_offset 2022 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2023 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); crtc_offset 2024 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); crtc_offset 2026 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2027 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2028 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); crtc_offset 2030 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); crtc_offset 2031 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); crtc_offset 2033 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); crtc_offset 2038 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, crtc_offset 2044 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2048 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2051 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2054 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2058 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); crtc_offset 2062 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2177 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); crtc_offset 2182 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); crtc_offset 2190 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2200 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, crtc_offset 2202 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, crtc_offset 2205 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, crtc_offset 2235 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); crtc_offset 2236 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); crtc_offset 2237 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, crtc_offset 2600 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; crtc_offset 106 drivers/gpu/drm/r128/r128_drv.h u32 crtc_offset; crtc_offset 1236 drivers/gpu/drm/r128/r128_state.c dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); crtc_offset 1255 drivers/gpu/drm/r128/r128_state.c R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); crtc_offset 1394 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); crtc_offset 1396 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, crtc_offset 1398 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, crtc_offset 1400 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 1402 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 1404 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); crtc_offset 1405 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); crtc_offset 1412 drivers/gpu/drm/radeon/atombios_crtc.c WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, crtc_offset 1419 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); crtc_offset 1420 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); crtc_offset 1421 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); crtc_offset 1422 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); crtc_offset 1423 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); crtc_offset 1424 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); crtc_offset 1427 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); crtc_offset 1428 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); crtc_offset 1431 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, crtc_offset 1434 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, crtc_offset 1438 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, crtc_offset 1445 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, crtc_offset 1449 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); crtc_offset 1609 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); crtc_offset 1620 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 1623 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset, (u32) fb_location); crtc_offset 1624 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); crtc_offset 1626 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); crtc_offset 1629 drivers/gpu/drm/radeon/atombios_crtc.c WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, crtc_offset 1635 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); crtc_offset 1636 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); crtc_offset 1637 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); crtc_offset 1638 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); crtc_offset 1639 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); crtc_offset 1640 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); crtc_offset 1643 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); crtc_offset 1644 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); crtc_offset 1646 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, crtc_offset 1650 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, crtc_offset 1654 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, crtc_offset 1658 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); crtc_offset 2181 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); crtc_offset 2183 drivers/gpu/drm/radeon/atombios_crtc.c WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); crtc_offset 2246 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; crtc_offset 2249 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; crtc_offset 2252 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; crtc_offset 2255 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; crtc_offset 2258 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; crtc_offset 2261 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; crtc_offset 2266 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = crtc_offset 2269 drivers/gpu/drm/radeon/atombios_crtc.c radeon_crtc->crtc_offset = 0; crtc_offset 2087 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, crtc_offset 2090 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); crtc_offset 2093 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, crtc_offset 2096 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); crtc_offset 2099 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, crtc_offset 2102 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); crtc_offset 8805 drivers/gpu/drm/radeon/cik.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 8855 drivers/gpu/drm/radeon/cik.c WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, crtc_offset 9353 drivers/gpu/drm/radeon/cik.c wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); crtc_offset 9357 drivers/gpu/drm/radeon/cik.c WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 9358 drivers/gpu/drm/radeon/cik.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, crtc_offset 9362 drivers/gpu/drm/radeon/cik.c tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); crtc_offset 9365 drivers/gpu/drm/radeon/cik.c WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 9366 drivers/gpu/drm/radeon/cik.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, crtc_offset 9370 drivers/gpu/drm/radeon/cik.c WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); crtc_offset 1348 drivers/gpu/drm/radeon/evergreen.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 1424 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, crtc_offset 1426 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, crtc_offset 1428 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 1431 drivers/gpu/drm/radeon/evergreen.c RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); crtc_offset 1447 drivers/gpu/drm/radeon/evergreen.c return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & crtc_offset 1682 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); crtc_offset 1684 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 1707 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); crtc_offset 1709 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 1867 drivers/gpu/drm/radeon/evergreen.c WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); crtc_offset 2304 drivers/gpu/drm/radeon/evergreen.c WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); crtc_offset 2305 drivers/gpu/drm/radeon/evergreen.c WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); crtc_offset 170 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); crtc_offset 174 drivers/gpu/drm/radeon/r100.c if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) crtc_offset 182 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); crtc_offset 200 drivers/gpu/drm/radeon/r100.c return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & crtc_offset 346 drivers/gpu/drm/radeon/r600.c WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 39 drivers/gpu/drm/radeon/radeon_cursor.c cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); crtc_offset 44 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); crtc_offset 46 drivers/gpu/drm/radeon/radeon_cursor.c cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); crtc_offset 51 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); crtc_offset 53 drivers/gpu/drm/radeon/radeon_cursor.c cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); crtc_offset 58 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); crtc_offset 68 drivers/gpu/drm/radeon/radeon_cursor.c WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, crtc_offset 72 drivers/gpu/drm/radeon/radeon_cursor.c WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, crtc_offset 99 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, crtc_offset 101 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 103 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); crtc_offset 117 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 119 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); crtc_offset 124 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, crtc_offset 218 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); crtc_offset 219 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); crtc_offset 220 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, crtc_offset 223 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); crtc_offset 224 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); crtc_offset 225 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, crtc_offset 234 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset, crtc_offset 238 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, crtc_offset 243 drivers/gpu/drm/radeon/radeon_cursor.c WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, crtc_offset 57 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); crtc_offset 59 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); crtc_offset 60 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); crtc_offset 61 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); crtc_offset 63 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); crtc_offset 64 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); crtc_offset 65 drivers/gpu/drm/radeon/radeon_display.c WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); crtc_offset 83 drivers/gpu/drm/radeon/radeon_display.c WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); crtc_offset 95 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); crtc_offset 97 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); crtc_offset 98 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); crtc_offset 99 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); crtc_offset 101 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); crtc_offset 102 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); crtc_offset 103 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); crtc_offset 105 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); crtc_offset 106 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); crtc_offset 108 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); crtc_offset 113 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, crtc_offset 132 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, crtc_offset 135 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, crtc_offset 137 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, crtc_offset 139 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, crtc_offset 143 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); crtc_offset 145 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); crtc_offset 146 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); crtc_offset 147 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); crtc_offset 149 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); crtc_offset 150 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); crtc_offset 151 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); crtc_offset 153 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); crtc_offset 154 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); crtc_offset 156 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); crtc_offset 161 drivers/gpu/drm/radeon/radeon_display.c WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, crtc_offset 167 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, crtc_offset 172 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, crtc_offset 175 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, crtc_offset 178 drivers/gpu/drm/radeon/radeon_display.c WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, crtc_offset 182 drivers/gpu/drm/radeon/radeon_display.c WREG32(0x6940 + radeon_crtc->crtc_offset, 0); crtc_offset 187 drivers/gpu/drm/radeon/radeon_display.c WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, crtc_offset 44 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); crtc_offset 45 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); crtc_offset 46 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); crtc_offset 384 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; crtc_offset 544 drivers/gpu/drm/radeon/radeon_legacy_crtc.c crtc_offset = (u32)base; crtc_offset 546 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); crtc_offset 554 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); crtc_offset 555 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); crtc_offset 556 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); crtc_offset 725 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); crtc_offset 726 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); crtc_offset 727 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); crtc_offset 728 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); crtc_offset 1122 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; crtc_offset 334 drivers/gpu/drm/radeon/radeon_mode.h uint32_t crtc_offset; crtc_offset 121 drivers/gpu/drm/radeon/rs600.c u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); crtc_offset 126 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); crtc_offset 129 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, crtc_offset 131 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 133 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 138 drivers/gpu/drm/radeon/rs600.c if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) crtc_offset 146 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); crtc_offset 154 drivers/gpu/drm/radeon/rs600.c return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & crtc_offset 327 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); crtc_offset 329 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 345 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); crtc_offset 347 drivers/gpu/drm/radeon/rs600.c WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); crtc_offset 714 drivers/gpu/drm/radeon/rv515.c int index_reg = 0x6578 + crtc->crtc_offset; crtc_offset 715 drivers/gpu/drm/radeon/rv515.c int data_reg = 0x657c + crtc->crtc_offset; crtc_offset 717 drivers/gpu/drm/radeon/rv515.c WREG32(0x659C + crtc->crtc_offset, 0x0); crtc_offset 718 drivers/gpu/drm/radeon/rv515.c WREG32(0x6594 + crtc->crtc_offset, 0x705); crtc_offset 719 drivers/gpu/drm/radeon/rv515.c WREG32(0x65A4 + crtc->crtc_offset, 0x10001); crtc_offset 720 drivers/gpu/drm/radeon/rv515.c WREG32(0x65D8 + crtc->crtc_offset, 0x0); crtc_offset 721 drivers/gpu/drm/radeon/rv515.c WREG32(0x65B0 + crtc->crtc_offset, 0x0); crtc_offset 722 drivers/gpu/drm/radeon/rv515.c WREG32(0x65C0 + crtc->crtc_offset, 0x0); crtc_offset 723 drivers/gpu/drm/radeon/rv515.c WREG32(0x65D4 + crtc->crtc_offset, 0x0); crtc_offset 811 drivers/gpu/drm/radeon/rv770.c u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); crtc_offset 816 drivers/gpu/drm/radeon/rv770.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); crtc_offset 819 drivers/gpu/drm/radeon/rv770.c WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, crtc_offset 828 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 830 drivers/gpu/drm/radeon/rv770.c WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, crtc_offset 835 drivers/gpu/drm/radeon/rv770.c if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) crtc_offset 843 drivers/gpu/drm/radeon/rv770.c WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); crtc_offset 851 drivers/gpu/drm/radeon/rv770.c return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & crtc_offset 2004 drivers/gpu/drm/radeon/si.c WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, crtc_offset 2435 drivers/gpu/drm/radeon/si.c arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); crtc_offset 2439 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); crtc_offset 2440 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, crtc_offset 2444 drivers/gpu/drm/radeon/si.c tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); crtc_offset 2447 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); crtc_offset 2448 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, crtc_offset 2452 drivers/gpu/drm/radeon/si.c WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); crtc_offset 2455 drivers/gpu/drm/radeon/si.c WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); crtc_offset 2456 drivers/gpu/drm/radeon/si.c WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); crtc_offset 191 drivers/video/fbdev/aty/radeonfb.h u32 crtc_offset;