crtc_enabled      479 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		int crtc_enabled, i;
crtc_enabled      485 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
crtc_enabled      487 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			if (crtc_enabled) {
crtc_enabled      505 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		int crtc_enabled, i;
crtc_enabled      511 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
crtc_enabled      513 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			if (crtc_enabled) {
crtc_enabled      376 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		int crtc_enabled, i;
crtc_enabled      382 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 			crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
crtc_enabled      384 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 			if (crtc_enabled) {
crtc_enabled      419 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		int crtc_enabled, i;
crtc_enabled      425 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 			crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
crtc_enabled      427 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 			if (crtc_enabled) {
crtc_enabled     2666 drivers/gpu/drm/radeon/evergreen.c 	u32 crtc_enabled, tmp, frame_count, blackout;
crtc_enabled     2679 drivers/gpu/drm/radeon/evergreen.c 		crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
crtc_enabled     2680 drivers/gpu/drm/radeon/evergreen.c 		if (crtc_enabled) {
crtc_enabled     2681 drivers/gpu/drm/radeon/evergreen.c 			save->crtc_enabled[i] = true;
crtc_enabled     2725 drivers/gpu/drm/radeon/evergreen.c 			save->crtc_enabled[i] = false;
crtc_enabled     2728 drivers/gpu/drm/radeon/evergreen.c 			save->crtc_enabled[i] = false;
crtc_enabled     2747 drivers/gpu/drm/radeon/evergreen.c 		if (save->crtc_enabled[i]) {
crtc_enabled     2786 drivers/gpu/drm/radeon/evergreen.c 		if (save->crtc_enabled[i]) {
crtc_enabled     2819 drivers/gpu/drm/radeon/evergreen.c 		if (save->crtc_enabled[i]) {
crtc_enabled      280 drivers/gpu/drm/radeon/radeon_asic.h 	bool crtc_enabled[2];
crtc_enabled      507 drivers/gpu/drm/radeon/radeon_asic.h 	bool crtc_enabled[RADEON_MAX_CRTCS];
crtc_enabled      300 drivers/gpu/drm/radeon/rv515.c 	u32 crtc_enabled, tmp, frame_count, blackout;
crtc_enabled      310 drivers/gpu/drm/radeon/rv515.c 		crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
crtc_enabled      311 drivers/gpu/drm/radeon/rv515.c 		if (crtc_enabled) {
crtc_enabled      312 drivers/gpu/drm/radeon/rv515.c 			save->crtc_enabled[i] = true;
crtc_enabled      335 drivers/gpu/drm/radeon/rv515.c 			save->crtc_enabled[i] = false;
crtc_enabled      338 drivers/gpu/drm/radeon/rv515.c 			save->crtc_enabled[i] = false;
crtc_enabled      365 drivers/gpu/drm/radeon/rv515.c 		if (save->crtc_enabled[i]) {
crtc_enabled      409 drivers/gpu/drm/radeon/rv515.c 		if (save->crtc_enabled[i]) {
crtc_enabled      451 drivers/gpu/drm/radeon/rv515.c 		if (save->crtc_enabled[i]) {