crtc5            7035 drivers/gpu/drm/radeon/cik.c 	u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
crtc5            7200 drivers/gpu/drm/radeon/cik.c 		crtc5 |= VBLANK_INTERRUPT_MASK;
crtc5            7255 drivers/gpu/drm/radeon/cik.c 		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);