crq_expansion_mode  554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
crq_expansion_mode  861 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
crq_expansion_mode  174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
crq_expansion_mode  213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
crq_expansion_mode  202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
crq_expansion_mode 1059 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
crq_expansion_mode  128 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
crq_expansion_mode  219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_regs->crq_expansion_mode = 1;
crq_expansion_mode  219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_regs->crq_expansion_mode = 1;
crq_expansion_mode  200 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_regs->crq_expansion_mode = 1;
crq_expansion_mode  500 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int crq_expansion_mode;
crq_expansion_mode  189 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 	dml_print("DML_RQ_DLG_CALC:    crq_expansion_mode  = 0x%0x\n", rq_regs.crq_expansion_mode);
crq_expansion_mode  256 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	rq_regs->crq_expansion_mode = 1;