DC_HPD_CONTROL    355 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
DC_HPD_CONTROL    394 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
DC_HPD_CONTROL    373 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
DC_HPD_CONTROL    411 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
DC_HPD_CONTROL   1373 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	uint32_t addr = HPD_REG(DC_HPD_CONTROL);
DC_HPD_CONTROL   1377 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
DC_HPD_CONTROL   1380 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN);
DC_HPD_CONTROL   1387 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	uint32_t addr = HPD_REG(DC_HPD_CONTROL);
DC_HPD_CONTROL   1390 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
DC_HPD_CONTROL     44 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	SRI(DC_HPD_CONTROL, HPD, id)
DC_HPD_CONTROL    113 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t DC_HPD_CONTROL;
DC_HPD_CONTROL   1356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	HPD_REG_UPDATE(DC_HPD_CONTROL,
DC_HPD_CONTROL   1364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	HPD_REG_UPDATE(DC_HPD_CONTROL,
DC_HPD_CONTROL     40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	SRI(DC_HPD_CONTROL, HPD, id)
DC_HPD_CONTROL     81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 	uint32_t DC_HPD_CONTROL;